TP3420AV National Semiconductor, TP3420AV Datasheet - Page 3

• Manufacturer Part Number: TP3420AV
• Manufacturer: National Semiconductor

Specifications of TP3420AV

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Pin Descriptions
FS
FS
(Pin 11)
B
B
DEN
(Pin 8)
CI
x
r
Name
a
b
x
/p2
In NT modes and TES mode, this pin is
the Transmit Frame Sync pulse
TTL/CMOS input, requiring a positive
edge to indicate the start of the active
channel time for transmit “B” and “D”
channel data into B
this pin is a digital output pulse whose
positive indicates the start of the “B”
channel data transfer at both B
In NT modes and TES mode, this pin is
the Receive Frame Sync pulse
TTL/CMOS input, requiring a positive
edge to indicate the start of the active
channel time of the device for receive “B”
and “D” channel data out from B
mode only, when digital interface Format
1 is selected, this pin is an 8-bit wide
pulse which indicates the active slot for
the B2 channel on the digital interface.
The DCKE command will alter the
function of this pin. See Table 2 for
details.
TTL/CMOS input for “B” and “D” channel
data to be transmitted to the line; must be
synchronous with BCLK.
CMOS output for “B” and “D” channel
data received from the line, which is
synchronous with BCLK. When not
shifting data, this pin is TRI-STATE
In TEM mode, this pin by default is a
CMOS output which is normally low and
pulses high to indicate the active bit-times
for “D” channel Transmit data at the B
input. It is intended to be gated with
BCLK to control the shifting of data from
layer 2 device to the TP3420A transmit
buffer.
In NT modes, this pin by default is a
pulse output (DEN
every 8 KHz frame and indicates the
location of D channel data input on the B
pin.
In TES mode, this pin by default is an
output synchronized clock (SCLK) at the
frequency selected by the Digital
Interface Format. This clock is
phase-locked to the received line signal,
and is intended to be used as the BCLK
source.
This pin called P2 in Table 1 can also be
programmed to provide alternate
functions. See Table 1 for details.
MICROWIRE control channel serial data
TTL/CMOS input.
(Continued)
Description
x
) which occurs in
x
. In TEM mode only,
x
r
and B
. In TEM
®
.
x
r
.
x
3
Note 1: Crystal specification: 15.36 MHz parallel resonant; R
C
Note 2: The 33 pF includes any board capacitance.
ALTERNATE PIN FUNCTIONS
With a MICROWIRE command PINDEF (B'1110 0 x2 x1 x0)
the pin signal functions of these pins can be changed to pro-
vide alternate functions (see Table 1 and the MICROWIRE
command in Table 4 ). “
ter a device mode selection. Power-up default device mode
is NTA.
CO
CCLK
CS
INT
LSD/P1
(Pin 18)
L
L
L
o
i
+, L
= 20 pF and C
+, L
Name
i
−
o
−
O
Control channel serial data CMOS output
for status information. When not enabled
by CS, this output is TRI-STATE.
TTL/CMOS clock input for the Control
Channel.
Chip Select input which enables the
control channel data to be shifted in and
out when pulled low. When high, this pin
inhibits the Control interface.
Interrupt output, a latched n-channel
open-drain output signal which is
normally high impedance, and goes low
to indicate a change of status of the loop
transmission system.
In all modes, this pin by default is the
Line Signal Detect output, an n-channel
open-drain output which is normally
high-impedance, but pulls low when the
device is powered down and a received
line signal is detected. It is intended to be
used to “wake-up” a microprocessor from
a low-power idle mode. This output is
high impedance when the device is
powered up.
This pin P1 in Table 1 can also be
programmed to provide alternate
functions. See Table 1 for details.
Transmit AMI signal differential outputs to
the line transformer. When used with a
2:1 step-down transformer, the line signal
conforms to the output pulse masks in
I.430.
Receive AMI signal differential inputs
from the line transformer. The L
also the internal voltage reference pin,
and must be decoupled to GND with a 10
µf capacitor in parallel with a 0.1 µF
ceramic capacitor.
<
7 pF.
*
” indicates the default pin function af-
Description
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i
− pin is
s
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