TP3420AV National Semiconductor, TP3420AV Datasheet - Page 18

• Manufacturer Part Number: TP3420AV
• Manufacturer: National Semiconductor

Specifications of TP3420AV

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

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Functional Description
EBIT0 command forces the E bit to 0 continuously to simu-
late the effect of a busy D channel. The D channel access al-
gorithm can be verified by releasing the E-bit control using
the EBITNRM command. Alternatively, it is possible to invert
the outgoing E-bit from the actual computed E-bit within the
NT (EBITI). This method too has the effect of forcing the
D-channel to appear busy. The EBITNRM command is again
used to set the E-bit control back to normal condition.
INVERT B1 AND B2 DATA CHANNELS TO OPERATE
OVER RESTRICTED FACILITIES
On “restricted” network transmission facilities (such as cer-
tain T1 links), the transmission of an “all ZEROs” octet is not
permitted. So, the data originating from a TE has to be re-
stricted.
The HDLC protocol inherently restricts the number of con-
tiguous “1”s to 7, as in the abort character (11111110). An idle
HDLC channel is filled with “1”s, repeated aborts or repeated
flags (01111110). On operation over restricted facilities, the
idle character must NOT be continuous “1”s, but can be
aborts or flag characters. This ensures that the maximum
contiguous “1”s is restricted to 7. By inverting the entire
HDLC bit stream (“1”s with “0”s), the data contains a maxi-
mum of 7 contiguous “0”s which can then be transferred
across the network having restricted facility links.
Data in each of the B channels can be inverted indepen-
dently with the use of the INVB1 and INVB2 commands. The
data is inverted in both transmit and receive directions in a B
channel. The NRMB12 command resets the B1 and B2
channel data stream to normal operation. The D channel
data is always considered to be using unrestricted facilities
and does not need to provide an inverted bit stream.
MULTIFRAME MAINTENANCE CHANNELS
(SC1, SC2 AND Q WORDS)
Each direction of transmission across the S interface in-
cludes low-speed (800 bit/s) channels for loop maintenance,
accessed through the control interface of the TP3420A. A
multiframe structure, consisting of 20 frames on the S inter-
face, is used to synchronize these channels and convey
messages coded into 4-bit words, see Table 8 . One word is
transmitted downstream (NT-to-TE) in the SC1 sub-channel
1, and one word is transmitted upstream (TE-to-NT) in the
complementary Q channel every multiframe. There are 4 ad-
ditional sub-channels (each of 800 bits/s) SC2, SC3, SC4
and SC5 allocated in the downstream direction.
The 1991 version of ANSI T1.605 defines the use of only the
SC1 and SC2 in the NT to TE direction (Section 8.6 of ANSI
T1.605-1991), and the Q channel in the TE to NT direction. It
also adds a distinction between high and low priority mes-
sages in the SC1/Q channel. The SC1/Q channels are
complementary channels used to perform loop maintenance
functions. The Q channel is used by a TE to request mainte-
nance modes (such as loopbacks) and the SC1 channel is
used by the NT to respond to the requests. Messages trans-
ferred through these channels must be assigned either as
high priority or low priority, which determines the order of
transmission. The TP3420A provides hardware support to
handle these messages. SC2 is an additional information
channel in the NT to TE direction, supplying line condition
status of the network to the TEs.
The use of any of the channels is optional and may be en-
abled individually.
(Continued)
18
CONTROL OF MULTIFRAMING CLOCK AND
INDICATION
With the device in NT mode, the MIE1 (or the MIE2) com-
mand enables the transmission of the Multiframe identifica-
tion algorithm (reversal of the FA/N bits every 5th frame and
the M bit set to “1” every 20th frame) and enables the MFR1
(or the MFR2) interrupts. The algorithm is present during
INFO 2 and INFO 4 frames. In TE modes the MIE1 (or the
MIE2) command only enables the MFR1 (or the MFR2) inter-
rupt, since the device will always search for and synchronize
to the multiframing identification bits if the NT is sending
them.
The MID1 and MID2 commands disable the transmission of
the Multiframe identification algorithm in NT mode and dis-
able the MFR1 and MFR2 interrupts in both NT and TE
modes. The MIE1, MIE2, MID1 and MID2 commands should
only be written to the device when it is deactivated (either
power-up or powered down). The Multiframe Transmit Reg-
isters should also be loaded with the appropriate “Idle” mes-
sages before activation, by means of the MFT1L and MFT2
instructions.
VALIDATION OF RECEIVED MULTIFRAME MESSAGES
The TP3420A includes logic to validate incoming SC1/Q and
SC2 messages for the specified number of consecutive re-
ceptions before generating the MFR1 or MFR2 interrupts.
The validation of the received messages is enabled with
ENV command and disabled with the DISV command. If en-
abled by the ENV command, at the end of each multiframe
the received 4-bit word is decoded to determine if it should
generate an MFR1 interrupt immediately, or be stored until 3
consecutive multiframes have contained the same 4-bit
word.
The validation algorithm implemented in the TP3420A con-
forms to the ANSI T1.605-1991 specification and is indicated
in Table 8 . When a 3x message is received an interrupt is
generated after 3 complete consecutive and identical multi-
frame words have been received. No more interrupts will be
generated until the received message changes. Some mes-
sages (such as FECV, LOP) have to be validated only once
to generate the MFR1 interrupt. All undefined codes in
SC1/Q are validated 1 time and reported to the CPU with the
MFR1 interrupt. All SC2 messages (defined or undefined)
are validated 3 times before generating the MFR2 interrupt.
If the 3x checking is disabled by the DISV command, a
change in the received SC1, SC2 or Q word generates
MFR1 or MFR2 interrupts.
Note, however, that no other action is taken by the TP3420A
in response to received SC1, SC2 or Q channel codes (e.g.
loopbacks are not automatically implemented); the external
controller must take the necessary action. This provides the
freedom to implement maintenance functions without con-
straints from the device, and to use the unassigned codes for
other functions.
SC1/Q Transmit Registers
For both NT and TE modes, the TP3420A has two registers
to transmit a SC1/Q channel message through two MI-
CROWIRE commands: MFT1L and MFT1H. Normally the
message in MFT1L is transmitted continually. However a
high priority message may be loaded in the MFT1H register
and transmitted once only. The MFT1H register is double
buffered so that it can accept two message loads within 5
ms, but not more than 3 messages within 10 ms.