TP3420AV National Semiconductor, TP3420AV Datasheet - Page 5

• Manufacturer Part Number: TP3420AV
• Manufacturer: National Semiconductor

Specifications of TP3420AV

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

Functional Description
boundary, by using a 0
dicate the start of a frame, and forcing the first binary zero
following the balance bit to be of the same polarity as the bal-
ance bit.
In the Network Termination (NT) to the Terminal Equipment
(TE) transmission direction the frame contains an echo
channel, the E bit, which is used to retransmit the D bits that
are received from the TE. The last bit of this frame is used as
a frame balancing bit. In the TE to NT direction,
d.c.-balancing is carried out for each channel, as illustrated
in Figure 2 .
LINE TRANSMIT SECTION
The differential line-driver outputs, L
signed to drive a transformer with an external termination re-
sistor. A suitable 2:1 transformer, terminated in 50 , results
in a signal amplitude of nominally 750 mV pk on the line
which fully complies with the I.430 pulse mask specifica-
tions. When driving a binary 1 symbol the output presents a
high impedance in accordance with I.430. When driving a 0+
or 0− symbol a voltage-limited current source is turned on.
Short-circuit protection is included in the output stage;
over-voltage protection is required externally, see the Appli-
cations section.
LINE RECEIVE SECTION
The receive input signal should be derived via a 1:1 trans-
former, or a 1:2 transformer of the same type used for the
transmit direction. At the front-end of the receive section is a
continuous filter which limits the noise bandwidth. To correct
pulse attenuation and distortion caused by the transmission
line in point-to-point and extended passive bus applications,
an adaptive equalizer enhances the received pulse shape,
+
bit followed by a 0
o
+ and L
(Continued)
FIGURE 1. Inverted AMI Line-Coding Rule
−
balance bit to in-
o
−, are de-
5
thereby restoring a “flat” channel response with maximum
eye opening over a wide spread of cable attenuation charac-
teristics. This equalizer is always enabled when either TE
mode or NT Mode Adaptive Sampling is selected, but is dis-
abled for short passive bus applications when NT Mode
Fixed Sampling is selected. An adaptive threshold circuit
maximizes the Signal-to-Noise ratio in the eye at the detec-
tor for all loop conditions.
In NTF mode the receive baud sampling point is fixed rela-
tive to the transmit baud clock. This ensures accurate sam-
pling of received pulses with differential delays on a passive
bus, thus extending the short passive bus range to over
250m of low capacitive cable.
In NTA and TE modes, the receive baud sampling is adap-
tive. In these modes, a DPLL (Digital Phase-Locked Loop)
recovers a low-jitter clock for optimum sampling of the re-
ceived symbols. The MCLK input provides the reference
clock for the DPLL at 15.36 MHz. Clocks for the digital inter-
face timing may either be derived from this recovered clock,
as in TE mode Digital System Interface Master, or may be
slaved to an external source, as in the T-interface side of an
NT-2 (TES mode). In TES and NT modes, re-timing circuitry
on the TP3420A allows the MCLK frequency to be plesio-
chronous (i.e., free-running) with respect to the network
clock, i.e. the 8 kHz FS
oscillator of 15.36 MHz
DPLL allows the network clock frequency to deviate up to
When the device is powered-down (either on initial
powering-on of the device or after using a PDN command), a
Line-Signal Detect circuit is enabled to detect the presence
of incoming data if the far-end starts to activate the loop. The
LSD circuit is disabled by a Power-Up (PUP) command.
±
50 ppm from nominal.
a
input. With a tolerance on the MCLK
±
100 ppm, the lock-in range of the
DS009143-4
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