TP3420AV National Semiconductor, TP3420AV Datasheet - Page 4

• Manufacturer Part Number: TP3420AV
• Manufacturer: National Semiconductor

Specifications of TP3420AV

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Package Type: PLCC
• Lead Free Status / Rohs Status: Not Compliant

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Pin Descriptions
PINDEF command is coded as X’EX (i.e. 11100x
Note 3: Default pin function after device mode selection.
SIGNAL DESCRIPTION
SCLK is an output synchronized clock at the frequency se-
lected by the Digital Interface Format. This clock is
phase-locked to the received line signal, and is intended to
be used as the BCLK source.
LSD is the Line Signal Output, an n-channel open-drain out-
put that is normally high-impedance, but pulls low when the
device is powered down and a received line signal is de-
tected. It is intended to be used to “wake-up” a microproces-
sor from a low-power idle mode. This output is a high imped-
ance when the device is powered up.
DENr is a CMOS output that is normally low and pulses high
to indicate the active bit times for “D” channel Receive data
at the B
control the shifting of data from the TP3420A receive buffer
to a layer 2 device.
DENx is a CMOS output that is normally low and pulses high
to indicate the active bit times for D channel Transmit data at
the B
the shifting of data from a layer 2 device to the TP3420A’s
transmit buffer. In NT mode, this pulse occurs every 8 kHz
frame and indicates the location of D channel data input on
the B
ADDITIONAL PIN CONFIGURATION
The TP3420A in TEM mode can be configured to interface
with the Motorola layer-2 devices such as the MC68302 and
the MC145488. A PINDEF (X’E1) command followed by a
DCKE (X’F1) command will alter the TP3420A pin functions
as shown in Table 2 . Other configurations of PINDEF are not
supported.
Device
TEM
TES
NTA
NTF
MMA
Mode
x
x
TABLE 1. Alternate Pin Function Assignment
input. It is intended to be gated with BCLK to control
pin.
r
output pin. It is intended to be gated with BCLK to
DENx
(Note 3)
SCLK
DENx
SCLK
(Note 3)
DENx
(Note 3)
SCLK
DENx
(Note 3)
SCLK
Function
P2 - Pin 8
(Note 3)
(Note 3)
(Note 3)
(Note 3)
x
0
1
0
1
0
1
0
1
2
(Continued)
Function
SCLK
DENx
SCLK
DENx
SCLK
DENx
SCLK
DENx
DENr
DENr
DENr
DENr
LSD
LSD
LSD
LSD
2
x
1
P1 - Pin 18
x
0
).
(Note 3)
(Note 3)
(Note 3)
(Note 3)
x
1
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
, x
0
4
Where:
• DCLK is a burst clock output intended to be used as a
• TxD is an input being sampled on the rising edge of
• DRCK is a burst clock output which pulses 2 BCLK peri-
Functional Description
DEVICE MODES
The TP3420A can be programmed into one of four possible
modes. For NT applications select NT Adaptive timing (NTA)
for all wiring configurations except a Short Passive Bus, for
which NT Fixed Timing (NTF) should be selected. In TE ap-
plications, select TE Master mode (TEM) for the device to be
the master (source) of clocks at the digital interface, or select
TE Slave mode (TES) for the digital interface to accept
clocks from the system.
Selection of these modes is described in the section on Con-
trol Register instructions.
POWER-ON DEVICE CONDITIONS
Following the initial application of power, the TP3420A SID
enters the power-down (de-activated) state, in which all the
internal circuits including the Master oscillator are inactive
and in a low power state except for the Line-Signal Detect
circuit; the line outputs L
state and the Digital System Interface is inactive. All bits in
the Control Register power-up as indicated in Table 1 . In
both NT and TE modes, a Line-Signal Detect circuit monitors
the line while the device is powered-down, to enable loop
transmission to be initiated from either end.
POWER-OFF DEVICE CONDITION
When power to the TP3420A is turned off, the Line outputs
L
passive bus lost power its transmit impedance still meets the
specification without any external relay (see AN665 for exter-
nal protection components). The receiver impedance also
remains in specification.
LINE CODING AND FRAME FORMAT
For both directions of transmission, Alternate-Mark Inversion
(AMI) coding with inverted binary is used, as illustrated in
Figure 1 . This coding rule requires that a binary ONE is rep-
resented by 0V high impedance output, whereas a binary
ZERO is represented by a positive or negative-going 100%
duty-cycle pulse. Normally, binary ZEROs alternate in polar-
ity to maintain a d.c.-balanced line signal.
The frame format used in the TP3420A SID follows the
CCITT recommendation specified in I.430 and illustrated in
Figure 2 . Each complete frame consists of 48 bits, with a line
bit rate of 192 kb/s, giving a frame repetition rate of 4 kHz. A
violation of the AMI coding rule is used to indicate a frame
o
+/L
clock source for the transmitter of an HDLC device.
DCLK during the active D-channel timeslot.
ods every 8 kHz frame. This output is intended to be used
as a clock source for the receiver of an HDLC device. The
D-channel data at B
the DRCK.
o
− go into high impedance state, hence if a TE on a
Pin Number
11
18
8
r
is transmitted on the falling edge of
TABLE 2.
o
+/L
DTCK
TxD
DRCK
o
− are in a high impedance
Pin Function