PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 73

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

9.2.13
An Acknowledge sequence is enabled by setting the
Acknowledge
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the Acknowledge data bit
are presented on the SDA pin. If the user wishes to gen-
erate an Acknowledge, the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit before
starting an Acknowledge sequence. The baud rate gen-
erator then counts for one rollover period (T
the SCL pin is de-asserted high). When the SCL pin is
FIGURE 9-16:
9.2.14
A STOP bit is asserted on the SDA pin at the end of a
receive/transmit, by setting the Stop Sequence Enable
bit PEN (SSPCON2<2>). At the end of a receive/
transmit, the SCL line is held low after the falling edge
of the ninth clock. When the PEN bit is set, the master
will assert the SDA line low. When the SDA line is sam-
pled low, the baud rate generator is reloaded and
counts down to 0. When the baud rate generator times
out, the SCL pin will be brought high, and one T
(baud rate generator rollover count) later, the SDA pin
will be de-asserted. When the SDA pin is sampled high
while SCL is high, the P bit (SSPSTAT<4>) is set. A
T
set (Figure 9-17).
© 2006 Microchip Technology Inc.
BRG
later, the PEN bit is cleared and the SSPIF bit is
ACKNOWLEDGE SEQUENCE
TIMING
STOP CONDITION TIMING
SSPIF
Note: T
sequence
Acknowledge sequence starts here.
SDA
SCL
ACKNOWLEDGE SEQUENCE WAVEFORM
Set SSPIF at the end
of receive
BRG
= one baud rate generator period.
ACKEN = 1, ACKDT = 0
enable
Write to SSPCON2,
bit,
8
D0
BRG
ACKEN
), and
BRG
Cleared in
software
T
BRG
ACK
sampled high (clock arbitration), the baud rate genera-
tor counts for T
lowing this, the ACKEN bit is automatically cleared, the
baud rate generator is turned off, and the SSP module
then goes into IDLE mode (Figure 9-16).
9.2.13.1
If the user writes the SSPBUF when an acknowledge
sequence is in progress, the WCOL is set and the con-
tents of the buffer are unchanged (the write doesn’t
occur).
Whenever the firmware decides to take control of the
bus, it will first determine if the bus is busy by checking
the S and P bits in the SSPSTAT register. If the bus is
busy, then the CPU can be interrupted (notified) when
a STOP bit is detected (i.e., bus is free).
9.2.14.1
If the user writes the SSPBUF when a STOP sequence
is in progress, then WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
T
BRG
9
Set SSPIF at the end
of Acknowledge sequence
ACKEN automatically cleared
WCOL Status Flag
WCOL Status Flag
BRG
. The SCL pin is then pulled low. Fol-
Cleared in
software
PIC16F872
DS30221C-page 71