PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 103

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

FIGURE 11-11:
11.14 In-Circuit Debugger
When the DEBUG bit in the configuration word is
programmed to a '0', the In-Circuit Debugger function-
ality is enabled. This function allows simple debugging
functions when used with MPLAB
microcontroller has this feature enabled, some of the
resources are not available for general use. Table 11-8
shows which features are consumed by the back-
ground debugger.
TABLE 11-8:
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/V
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip or one of
the third party development tool companies.
© 2006 Microchip Technology Inc.
I/O pins
Stack
Program Memory
Data Memory
Note
OSC1
CLKOUT
INT pin
INTF Flag
(INTCON<1>)
GIE bit
(INTCON<7>)
INSTRUCTION FLOW
Instruction
Fetched
Instruction
Executed
1:
2:
3:
4:
(4)
PC
XT, HS or LP oscillator mode assumed.
T
GIE = '1' assumed. In this case, after wake- up, the processor jumps to the interrupt routine.
If GIE = '0', execution will continue in-line.
CLKOUT is not available in these osc modes, but shown here for timing reference.
OST
Inst(PC) = SLEEP
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
= 1024T
Inst(PC - 1)
DEBUGGER RESOURCES
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
OSC
0x070 (0x0F0, 0x170, 0x1F0)
Address 0000h must be NOP
(drawing not to scale). This delay will not be there for RC osc mode.
Last 100h words
0x1EB - 0x1EF
Inst(PC + 1)
SLEEP
PC+1
RB6, RB7
1 level
®
IDE. When the
PP
, V
Processor in
SLEEP
DD
, GND,
PC+2
T
OST (2)
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Inst(PC + 2)
Inst(PC + 1)
11.15 Program Verification/Code
If the code protection bit(s) have not been pro-
grammed, the on-chip program memory can be read
out for verification purposes.
11.16 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are read-
able and writable during program/verify. It is recom-
mended that only the 4 Least Significant bits of the ID
location are used.
PC+2
Protection
Interrupt Latency
Dummy cycle
(Note 2)
PC + 2
PIC16F872
Inst(0004h)
Dummy cycle
0004h
DS30221C-page 101
Inst(0005h)
Inst(0004h)
0005h