PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 160

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F872
Code Protection ........................................................ 87
Compare Mode
Computed GOTO ............................................................... 20
Configuration Bits .............................................................. 87
Configuration Word ............................................................ 88
Conversion Considerations .............................................. 155
D
D/A Bit ................................................................................ 52
Data EEPROM ................................................................... 23
Data Memory ....................................................................... 7
Data/Address Bit (D/A) ...................................................... 52
DC and AC Characteristics Graphs and Tables .............. 139
DC Characteristics
Development Support ...................................................... 111
Device Overview .................................................................. 3
Direct Addressing .............................................................. 21
E
EECON1 and EECON2 Registers ..................................... 23
EECON1 Register .............................................................. 11
EECON2 Register .............................................................. 11
Electrical Characteristics ................................................. 117
Equations
Errata ................................................................................... 2
External Clock Timing Requirements .............................. 127
F
Firmware Instructions ...................................................... 103
FLASH Program Memory .................................................. 23
FSR Register ................................................................ 9
G
GCEN Bit
General Call Address Support ........................................... 61
DS30221C-page 158
CCP Pin Configuration ............................................... 47
Timer1 Mode Selection .............................................. 47
Associated Registers ................................................. 28
Code Protection ......................................................... 28
Reading ..................................................................... 25
Special Functions Registers ...................................... 23
Spurious Write Protection .......................................... 27
Write Verify ................................................................ 27
Writing to .................................................................... 25
Bank Select (RP1:RP0 Bits) ........................................ 7
General Purpose Register File .................................... 7
Register File Map ......................................................... 8
Special Function Registers .......................................... 9
Commercial and Industrial ............................... 119–122
Extended ............................................................ 123–52
A/D
Associated Registers ................................................. 28
Code Protection ......................................................... 28
Configuration Bits and Read/Write State ................... 28
Reading ..................................................................... 26
Special Function Registers ........................................ 23
Spurious Write Protection .......................................... 27
Write Protection ......................................................... 28
Write Verify ................................................................ 27
Writing to .................................................................... 26
General Call Enable Bit (GCEN) ................................ 54
Calculating Acquisition Time ............................. 82
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I
I/O Ports ............................................................................ 29
I
I
ICEPIC In-Circuit Emulator .............................................. 112
ID Locations ..............................................................87
In-Circuit Debugger ...................................................87
In-Circuit Serial Programming (ICSP) .......................87
INDF Register ...................................................................... 9
Indirect Addressing ............................................................ 21
Instruction Format ........................................................... 103
Instruction Set ................................................................. 103
2
2
C Bus
C Mode
Connection Considerations ....................................... 78
Sample Device Configuration .................................... 78
Acknowledge Sequence Timing ................................ 71
Addressing ................................................................ 59
Associated Registers ................................................. 62
Baud Rate Generator (BRG) ..................................... 64
Bus Arbitration ........................................................... 73
Bus Collision .............................................................. 73
Clock Arbitration ........................................................ 72
Conditions to not give ACK Pulse ............................. 59
Effects of a RESET .............................................62
General Call Address Support ................................... 61
Master Mode ............................................................. 63
Master Mode Operation ............................................. 64
Master Mode Reception ............................................ 69
Master Mode Repeated START Condition ................ 66
Master Mode START Condition ................................ 65
Master Mode Transmission ....................................... 67
Master Mode Transmit Sequence ............................. 64
Multi-Master Communication ..................................... 73
Multi-Master Mode ..................................................... 63
Operation ................................................................... 58
Slave Mode ............................................................... 58
Slave Reception ........................................................ 59
Slave Transmission ................................................... 60
SLEEP Operation ................................................62
SSPADD Address Register ....................................... 58
SSPBUF Register ...................................................... 58
STOP Condition Timing ............................................. 71
FSR Register .........................................................7
ADDLW ................................................................... 105
ADDWF ................................................................... 105
ANDLW ................................................................... 105
ANDWF ................................................................... 105
BCF ......................................................................... 105
BSF ......................................................................... 105
BTFSC ..................................................................... 105
BTFSS ..................................................................... 105
CALL ....................................................................... 106
CLRF ....................................................................... 106
CLRW ...................................................................... 106
CLRWDT ................................................................. 106
COMF ...................................................................... 106
DECF ....................................................................... 106
DECFSZ .................................................................. 107
GOTO ...................................................................... 107
INCF ........................................................................ 107
INCFSZ ................................................................... 107
IORLW ..................................................................... 107
IORWF .................................................................... 107
Repeated START Condition .............................. 76
START Condition .............................................. 74
STOP Condition ................................................ 77
© 2006 Microchip Technology Inc.
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