PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 66

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F872
9.2.7
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON and by setting the
SSPEN bit. Once Master mode is enabled, the user
has six options.
• Assert a START condition on SDA and SCL.
• Assert a Repeated START condition on SDA and
• Write to the SSPBUF register, initiating transmis-
• Generate a STOP condition on SDA and SCL.
• Configure the I
• Generate an Acknowledge condition at the end of
9.2.7.1
The master device generates all of the serial clock
pulses and the START and STOP conditions. A trans-
fer is ended with a STOP condition or with a Repeated
START condition. Since the Repeated START condi-
tion is also the beginning of the next serial transfer, the
I
In Master Transmitter mode, serial data is output
through SDA, while SCL outputs the serial clock. The
first byte transmitted contains the slave address of the
receiving device (7 bits) and the Read/Write (R/W) bit.
In this case, the R/W bit will be logic '0'. Serial data is
transmitted 8 bits at a time. After each byte is transmit-
ted, an Acknowledge bit is received. START and STOP
conditions are output to indicate the beginning and the
end of a serial transfer.
In Master Receive mode, the first byte transmitted con-
tains the slave address of the transmitting device
(7 bits) and the R/W bit. In this case, the R/W bit will be
logic '1'. Thus, the first byte transmitted is a 7-bit slave
address followed by a '1' to indicate receive bit. Serial
data is received via SDA, while SCL outputs the serial
clock. Serial data is received 8 bits at a time. After each
byte is received, an Acknowledge bit is transmitted.
START and STOP conditions indicate the beginning
and end of transmission.
The baud rate generator used for SPI mode operation
is now used to set the SCL clock frequency for either
100 kHz, 400 kHz or 1 MHz I
rate generator reload value is contained in the lower 7
bits of the SSPADD register. The baud rate generator
DS30221C-page 64
2
C bus will not be released.
SCL.
sion of data/address.
a received byte of data.
Note:
The MSSP module, when configured in I
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
initiate transmission, before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
I
2
C MASTER MODE SUPPORT
I
2
C Master Mode Operation
2
C port to receive data.
2
C operation. The baud
2
C
will automatically begin counting on a write to the
SSPBUF. Once the given operation is complete (i.e.,
transmission of the last data bit is followed by ACK) the
internal clock will automatically stop counting and the
SCL pin will remain in its last state
A typical transmit sequence would go as follows:
a)
b)
c)
d)
e)
f)
g)
h)
i)
j)
k)
l)
9.2.8
In I
located in the lower 7 bits of the SSPADD register
(Figure 9-10). When the BRG is loaded with this value,
the BRG counts down to 0 and stops until another reload
has taken place. The BRG count is decremented twice
per instruction cycle (T
In I
If Clock Arbitration is taking place, for instance, the
BRG will be reloaded when the SCL pin is sampled
high (Figure 9-11).
FIGURE 9-10:
SSPM3:SSPM0
2
2
SSPM3:SSPM0
C Master mode, the BRG is reloaded automatically.
The user generates a Start Condition by setting
the START enable bit (SEN) in SSPCON2.
SSPIF is set. The module will wait the required
start time before any other operation takes place.
The user loads the SSPBUF with address to
transmit.
Address is shifted out the SDA pin until all 8 bits
are transmitted.
The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
The user loads the SSPBUF with eight bits of data.
DATA is shifted out the SDA pin until all 8 bits are
transmitted.
The MSSP module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF bit.
The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
Interrupt is generated once the STOP condition
is complete.
C Master mode, the reload value for the BRG is
SCL
BAUD RATE GENERATOR
CLKOUT
CY
BAUD RATE GENERATOR
BLOCK DIAGRAM
© 2006 Microchip Technology Inc.
), on the Q2 and Q4 clock.
Reload
Control
BRG Down Counter
SSPADD<6:0>
Reload
F
OSC
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