PIC16F872-I/SP Microchip Technology Inc., PIC16F872-I/SP Datasheet - Page 26

• Manufacturer Part Number: PIC16F872-I/SP
• Description: 28 PIN, 7 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F872-I/SP

• A/d Inputs: 5-Channel, 10-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16F872
Write operations have two control bits, WR and WREN,
and two status bits, WRERR and EEIF. The WREN bit
is used to enable or disable the write operation. When
WREN is clear, the write operation will be disabled.
Therefore, the WREN bit must be set before executing
a write operation. The WR bit is used to initiate the write
operation. It also is automatically cleared at the end of
the write operation. The interrupt flag EEIF (located in
register PIR2) is used to determine when the memory
write completes. This flag must be cleared in software
before setting the WR bit. For EEPROM Data memory,
once the WREN bit and the WR bit have been set, the
desired memory address in EEADR will be erased fol-
lowed by a write of the data in EEDATA. This operation
takes place in parallel with the microcontroller continu-
ing to execute normally. When the write is complete,
the EEIF flag bit will be set. For program memory, once
the WREN bit and the WR bit have been set, the micro-
controller will cease to execute instructions. The
REGISTER 3-1:
DS30221C-page 24
bit 7
bit 6-4
bit 3
bit 2
bit 1
bit 0
EECON1 REGISTER (ADDRESS 18Ch)
Legend:
S = Settable bit
U = Unimplemented bit, read as ‘0’
’1’ = Bit is set
bit 7
EEPGD: Program/Data EEPROM Select bit
1 = Accesses Program memory
0 = Accesses data memory
(This bit cannot be changed while a read or write operation is in progress.)
Unimplemented: Read as '0'
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
0 = The write operation completed
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
WR: Write Control bit
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit
0 = Write cycle to the EEPROM is complete
RD: Read Control bit
1 = Initiates an EEPROM read RD is cleared in hardware. The RD bit can only be set (not
0 = Does not initiate an EEPROM read
EEPGD
R/W-x
(any MCLR Reset or any WDT Reset during normal operation)
can only be set (not cleared) in software.)
cleared) in software.
U-0
—
U-0
R = Readable bit
’0’ = Bit is cleared
—
U-0
—
desired
EEADRH:EEADR will be erased. Then the data value
in EEDATH:EEDATA will be programmed. When com-
plete, the EEIF flag bit will be set and the microcontrol-
ler will continue to execute code.
The WRERR bit is used to indicate when the device
has been RESET during a write operation. WRERR
should be cleared after Power-on Reset. Thereafter, it
should be checked on any other RESET. The WRERR
bit is set when a write operation is interrupted by a
MCLR Reset or a WDT Time-out Reset during normal
operation. In these situations, following a RESET, the
user should check the WRERR bit and rewrite the
memory location if set. The contents of the data regis-
ters, address registers and EEPGD bit are not affected
by either MCLR Reset or WDT Time-out Reset during
normal operation.
WRERR
R/W-x
memory
x = Bit is unknown
W = Writable bit
- n = Value at POR
WREN
R/W-0
location
© 2006 Microchip Technology Inc.
R/S-0
WR
pointed
R/S-0
to
RD
bit 0
by