ADAU1381BCPZ Analog Devices Inc, ADAU1381BCPZ Datasheet - Page 6

• Manufacturer Part Number: ADAU1381BCPZ
• Description: IC AUDIO CODEC STEREO LN 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of ADAU1381BCPZ

• Data Interface: Serial, SPI™
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 100
• Dynamic Range, Adcs / Dacs (db) Typ: 96.5 / 100
• Voltage - Supply, Analog: 1.8 V ~ 3.65 V
• Voltage - Supply, Digital: 1.63 V ~ 3.65 V
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 100dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1381
Parameter
MICROPHONE BIAS
OUTPUT SIDE PERFORMANCE SPECIFICATIONS
Specifications guaranteed at 25°C (ambient). The output load for the speaker output path is an 8 Ω, 400 mW speaker.
Table 2.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
DAC TO LINE OUTPUT PATH
Dynamic Range
Beep Input Mute Attenuation
Offset Error
Gain Error
Interchannel Gain Mismatch
Beep Input PGA Gain Range
Beep Playback Mixer Gain Range
Power Supply Rejection Ratio
Bias Voltage
Bias Current Source
Noise in the Signal Bandwidth
DAC Resolution
Digital Attenuation Step
Digital Attenuation Range
Full-Scale Output Voltage (0 dB)
Line Output Mute Attenuation,
Line Output Mute Attenuation,
With A-Weighted Filter (RMS)
No Filter (RMS)
0.65 × AVDD
0.90 × AVDD
DAC to Mixer Path Muted
Line Output Muted
Test Conditions/Comments
−60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V; mute set by
Register 0x4008, Bit 3
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
AVDD = 3.3 V
CM capacitor = 10 μF
AVDD = 3.3 V, 100 mV p-p at 217 Hz
AVDD = 3.3 V, 100 mV p-p at 1 kHz
Microphone bias enabled
AVDD = 1.8 V, low bias
AVDD = 3.3 V, low bias
AVDD = 1.8 V, high bias
AVDD = 3.3 V, high bias
AVDD = 3.3 V, high bias, high
performance
AVDD = 3.3 V, 20 Hz to 20 kHz
High bias, high performance
High bias, low performance
Low bias, high performance
Low bias, low performance
AVDD = 1.8 V, 20 Hz to 20 kHz
High bias, high performance
High bias, low performance
Low bias, high performance
Low bias, low performance
Test Conditions/Comments
All DACs
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 3.3 V; mute set by Register
0x401C, Bit 5, and Register 0x401E, Bit 6
AVDD = 3.3 V; mute set by Register
0x4025, Bit 1, and Register 0x4026, Bit 1
Rev. B | Page 6 of 84
Min
−23
−15
Min
Typ
99
105
96
102
−90
10
−0.3
30
−58
−72
1.17
2.145
1.62
2.97
39
78
25
35
35
45
23
23
Typ
24
0.375
95
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
−85
−85
Max
+32
+6
5
Max
Unit
dB
dB
dB
dB
dB
mV
dB
mdB
dB
dB
dB
dB
V
V
V
V
mA
nV√Hz
nV√Hz
nV√Hz
nV√Hz
nV√Hz
nV√Hz
nV√Hz
nV√Hz
Unit
Bits
dB
dB
V rms
V rms (V p-p)
V rms (V p-p)
dB
dB