ADAU1381BCPZ Analog Devices Inc, ADAU1381BCPZ Datasheet
ADAU1381BCPZ
Specifications of ADAU1381BCPZ
Related parts for ADAU1381BCPZ
ADAU1381BCPZ Summary of contents
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FEATURES 24-bit stereo audio ADC and DAC 400 mW speaker amplifier (into 8 Ω load) Built-in sound engine for audio processing Wind noise detection and autofiltering Enhanced stereo capture (ESC) Dual-band automatic level control (ALC) 6-band equalizer, including notch filter ...
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ADAU1381 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications..................................................................................... 4 Record Side Performance Specifications................................... 4 Output Side Performance Specifications................................... 6 Power Supply Specifications........................................................ 8 Typical Power ...
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Pad Configuration.......................................................................70 Digital Subsystem Configuration..............................................77 REVISION HISTORY 1/11—Rev Rev. B Changes to Pin PDN Description in Table 10 .............................16 Changes to Power-Down Pin ( PDN ) Section..............................26 Changes to Table 23 ........................................................................36 3/10—Rev Rev. A Changes ...
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ADAU1381 SPECIFICATIONS Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications. Supply voltages AVDD = AVDD1 = AVDD2 = I/O supply = 3.3 V, digital supply = 1.5 V, unless otherwise noted; ...
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Parameter Left/Right Microphone PGA Gain Range Left/Right Microphone PGA Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio DIFFERENTIAL MICROPHONE INPUT TO ADC PATH Full-Scale Input Voltage (0 dB) Dynamic Range With A-Weighted Filter ...
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ADAU1381 Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Beep Input Mute Attenuation Offset Error Gain Error Interchannel Gain Mismatch Beep Input PGA Gain Range Beep Playback Mixer Gain Range Power Supply Rejection Ratio MICROPHONE BIAS Bias Voltage ...
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Parameter Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Total Harmonic Distortion + Noise Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Gain Error Interchannel Gain Mismatch Offset Error DAC TO SPEAKER OUTPUT PATH ...
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ADAU1381 Parameter Total Harmonic Distortion + Noise Dynamic Range With A-Weighted Filter (RMS) No Filter (RMS) Signal-to-Noise Ratio With A-Weighted Filter (RMS) No Filter (RMS) Power Supply Rejection Ratio Differential Offset Error Mono Mixer Mute Attenuation, Beep to Mixer Path ...
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TYPICAL POWER MANAGEMENT MEASUREMENTS Master clock = 12.288 MHz, PLL is active in integer mode at a 256 × f −1 dBFS with a frequency of 1 kHz. Analog input and output are simultaneously active. Pseudo differential stereo input is ...
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ADAU1381 Parameter DAC INTERPOLATION FILTER Pass Band Pass-Band Ripple Transition Band Stop Band Stop-Band Attenuation Group Delay DIGITAL INPUT/OUTPUT SPECIFICATIONS −25°C < T < +85°C, IOVDD = 1. 3.63 V, unless otherwise specified. A Table 6. Parameter HIGH ...
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DIGITAL TIMING SPECIFICATIONS −25°C < T < +85°C, IOVDD = 1. 3.63 V, unless otherwise specified. A Table 7. Digital Timing Parameter t MIN MASTER CLOCK Duty Cycle 30 SERIAL PORT t 10 BIL t ...
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ADAU1381 Digital Timing Diagrams t BIH BCLK t BIL t LIS LRCLK t SIS DAC_SDATA LEFT-JUSTIFIED MSB MODE t SIH DAC_SDATA MODE DAC_SDATA RIGHT-JUSTIFIED MODE 8-BIT CLOCKS (24-BIT DATA) 12-BIT CLOCKS (20-BIT DATA) 14-BIT CLOCKS (18-BIT DATA) ...
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CLS t CLATCH CCPH CCLK CDATA t CDS COUT t t SCH SDA t SCL CLK DATA1/ DATA2 DATA1 t CCPL t CDH Figure 4. SPI Port Timing SDR SDF t SCR SCLH ...
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ADAU1381 ABSOLUTE MAXIMUM RATINGS Table 8. Parameter Power Supply (AVDD1 = AVDD2) Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) Digital Input Voltage (Signal Pins) Operating Temperature Range (Case) Storage Temperature Range Stresses above those listed under Absolute ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 PDN 2 23 AGND2 INDICATOR AGND1 3 22 SPP AVDD1 ADAU1381 DVDDOUT 5 20 SPN TOP VIEW DGND 6 19 AVDD2 ...
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ADAU1381 Table 10. Pin Function Descriptions Pin No. LFCSP WLCSP Mnemonic PDN 3 B6 AGND1 4 C6 AVDD1 5 D6 DVDDOUT 6 E6 DGND 7 D5 GPIO 8 C4 SCL/CCLK 9 E5 SDA/COUT 10 C3 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 9. ADC Decimation Filter, 64× Oversampling, Normalized 0.04 0.02 0 –0.02 –0.04 ...
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ADAU1381 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 0 0.1 0.2 0.3 0.4 0.5 0.6 FREQUENCY (NORMALIZED TO Figure 15. DAC Interpolation Filter, 64× Oversampling, Normalized 0.20 0.15 0.10 0.05 0 –0.05 –0.10 ...
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SPEAKER OUTPUT POWER (mW) Figure 21. THD + N vs. Speaker Output Power, 8 Ω Load, 3.3 V Supply 0 –20 –40 –60 –80 –100 100 600 ...
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ADAU1381 SYSTEM BLOCK DIAGRAMS MICBIAS 0.1µF DIFFERENTIAL INPUT (LEFT) 10µF LMIC/LMICN/MICD1 49.9kΩ LMICP 10µF 49.9kΩ DIFFERENTIAL INPUT (RIGHT) 10µF RMIC/RMICN/MICD2 49.9kΩ RMICP 10µF 49.9kΩ 10µF BEEP EXTERNAL BEEP INPUT MCKI EXTERNAL 49.9Ω MCLK SOURCE 2.2pF MCKO 49.9Ω MCKO PDN PDN ...
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MICBIAS 0.1µF MICBIAS 0.1µF 2kΩ ANALOG LMIC/LMICN/MICD1 MIC 1 10µF CM 49.9kΩ LMICP MICBIAS 0.1µF 2kΩ ANALOG RMIC/RMICN/MICD2 MIC 2 10µF CM 49.9kΩ RMICP 10µF BEEP EXTERNAL BEEP INPUT MCKI EXTERNAL 49.9Ω MCLK SOURCE 2.2pF MCKO 49.9Ω MCKO PDN PDN ...
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ADAU1381 MICBIAS 0.1µF SINGLE-ENDED STEREO INPUT 10µF 1kΩ CM 49.9kΩ 10µF 1kΩ CM 49.9kΩ 10µF EXTERNAL BEEP INPUT EXTERNAL 49.9Ω MCLK SOURCE 2.2pF MCKO 49.9Ω PDN IOVDD AVDD1 10µF 10µF 10µF AVDD2 47µF 0.1µF 0.1µF 0.1µF 0.1µF SPN SPP AOUTL ...
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IOVDD 10µF 0.1µF MICBIAS 0.1µF BCLK OR MCLKO STEREO DIGITAL LMIC/LMICN/MICD1 MIC INPUT LMICP RMIC/RMICN/MICD2 1kΩ RMICP 10µF BEEP EXTERNAL BEEP INPUT MCKI EXTERNAL 49.9Ω MCLK SOURCE 2.2pF MCKO 49.9Ω MCKO PDN PDN Figure 26. System Block Diagram with Stereo ...
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ADAU1381 THEORY OF OPERATION The ADAU1381 is a low power audio codec with an integrated, fixed-function audio processing sound engine all-in-one package that offers high quality audio, low power, small size, and many advanced features. The stereo ...
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STARTUP, INITIALIZATION, AND POWER This section details the procedure for setting up the ADAU1381 properly. Figure 27 provides an overview of how to initialize the IC. START YES ARE AVDD1 AND AVDD2 CAN AVDD1 AND AVDD2 SUPPLIED SEPARATELY? BE SIMULTANEOUSLY ...
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ADAU1381 CLOCK GENERATION AND MANAGEMENT The ADAU1381 uses a flexible clocking scheme that enables the use of many different input clock rates. The PLL can be bypassed or used, resulting in two different approaches to clock manage- ment. For more ...
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CLOCKING AND SAMPLING RATES PLL CONTROL f /X MCKI INPUT DIVIDE INTEGER, NUMERATOR DENOMINATOR CORE CLOCK The core clock divider generates a core clock either from the PLL or directly from MCLK and can be set ...
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ADAU1381 Table 14 and Table 15 list the sampling rate divisions for common base sampling rates. Table 14. Base Sampling Rate Divisions for f Base Sampling Frequency Sampling Rate Scaling kHz ...
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The ADC and DAC sampling rate can be set in Register 16407 (0x4017), Converter Control 0, Bits[2:0], converter sampling rate. The sound engine sampling rate and serial port sampling rate are similarly set in Register 16619 (0x40EB), sound engine frame ...
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ADAU1381 RECORD SIGNAL PATH BEEP PGA LMIC/LMICN/ MICD1 LEFT PGA LMICP ADC CM RMIC/RMICN/ MICD2 RIGHT PGA RMICP ADC CM Figure 31. Record Signal Path Diagram INPUT SIGNAL PATH The ADAU1381 can be configured for three types of microphone inputs: ...
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LMIC/LMICN/ MICD1 PGA LMICP CM RMIC/RMICN/ MICD2 PGA RMICP CM Figure 34. Differential Input Configuration ANALOG-TO-DIGITAL CONVERTERS The ADAU1381 uses two 24-bit Σ-Δ analog-to-digital converters (ADCs) with selectable oversampling rates of either 64× or 128×. The full-scale input to the ...
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ADAU1381 PLAYBACK SIGNAL PATH LEFT PLAYBACK MIXER LEFT DAC LEFT PLAYBACK BEEP GAIN MONO PLAYBACK MONO BEEP GAIN PLAYBACK MIXER BEEP FROM RECORD PGA RIGHT PLAYBACK BEEP GAIN RIGHT DAC RIGHT PLAYBACK MIXER Figure 35. Playback Signal Path Diagram OUTPUT ...
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CONTROL PORTS The ADAU1381 can operate in one of two control modes: I control or SPI control. The ADAU1381 has both a 4-wire SPI control port and a 2-wire bus control port. Each can be used to ...
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ADAU1381 Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, the ADAU1381 immediately jumps to the idle condition. During a given ...
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I C Read and Write Operations Figure 40 shows the timing of a single-word write operation. Every ninth clock pulse, the ADAU1381 issues an acknowledge by pulling SDA low. Figure 41 shows the timing of a burst mode write ...
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ADAU1381 SPI PORT 2 By default, the ADAU1381 mode, but can be put into SPI control mode by pulling CLATCH low three times. The SPI port uses a 4-wire interface, consisting of CLATCH , CCLK, CDATA, ...
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CLATCH CCLK CDATA BYTE 0 Figure 44. SPI Write to ADAU1381 Clocking (Single-Write Mode) CLATCH CCLK CDATA BYTE 0 HIGH-Z COUT Figure 45. SPI Read from ADAU1381 Clocking (Single-Read Mode) BYTE 1 BYTE 1 BYTE 3 DATA Rev ...
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ADAU1381 SERIAL DATA INPUT/OUTPUT PORTS The flexible serial data input and output ports of the ADAU1381 can be set to accept or transmit data in 2-channel format 4-channel or 8-channel TDM stream to interface to external ADCs ...
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LEFT CHANNEL LRCLK BCLK SDATA MSB LEFT CHANNEL LRCLK BCLK MSB SDATA Figure 48. Left-Justified Mode—16 Bits to 24 Bits per Channel LEFT CHANNEL LRCLK BCLK SDATA MSB Figure 49. Right-Justified Mode—16 Bits to 24 Bits per Channel LRCLK BCLK ...
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ADAU1381 GENERAL-PURPOSE INPUT/OUTPUTS The serial data input/output pins are shared with the general- purpose input/output function. Each of these four pins can be set to only one function. The function of these pins is set in Register 16628 (0x40F4), serial ...
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SOUND ENGINE SIGNAL PROCESSING The ADAU1381 is designed to provide a fixed-function signal processing flow specifically catered to digital still cameras and other low power applications. PROCESSING FLOW The processing flow is outlined in Figure 52. PROGRAMMING Although the sound ...
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ADAU1381 APPLICATIONS INFORMATION POWER SUPPLY BYPASS CAPACITORS Each analog and digital power supply pin should be bypassed to its nearest appropriate ground pin with a single 100 nF capacitor. The connections to each side of the capacitor should be as ...
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CONTROL REGISTER MAP All registers except the PLL control register are 1-byte write and read registers. Table 27. Address Hex Decimal 0x4000 16384 0x4001 16385 0x4002 16386 0x4008 16392 0x4009 16393 0x400E 16398 0x400F 16399 0x4010 16400 0x4015 16405 0x4016 ...
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ADAU1381 CLOCK MANAGEMENT, INTERNAL REGULATOR, AND PLL CONTROL Register 16384 (0x4000), Clock Control The clock control register sets the clocking scheme for the ADAU1381. The system clock can be generated from either the PLL or directly from the MCKI (master ...
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Register 16385 (0x4001), Regulator Control Bits[2:1], Regulator Output Level These bits set the regulated voltage output for the digital core, DVDDOUT. After the initialization sequence has completed, the regulator output is set to 1.4 V. The recommended regulator output level ...
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ADAU1381 Table 32. PLL Control Register Bits Description [47:40] Denominator MSB 00000000 and 00000000: M[15:8] and M[7: … 00000000 and 11111101: M[15:8] and M[7:0] = 125 … 11111111 and 11111111: M[15:8] and M[7:0] = 65,535 [39:32] Denominator LSB ...
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Table 33. Fractional PLL Parameter Settings for f MCLK Input (MHz) Input Divider ( 14.4 1 19.2 1 19.68 1 19.8 1 Table 34. Fractional PLL Parameter Settings for f MCLK Input (MHz) Input Divider (X) ...
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ADAU1381 RECORD PATH CONFIGURATION Register 16392 (0x4008), Digital Microphone and Analog Beep Control This register controls the digital microphone settings and the analog beep input gain. Bits[5:4], Digital Microphone Enable These bits control the enable function for the stereo digital ...
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Register 16393 (0x4009), Record Power Management This register manages the power consumption for the record path. In particular, the current distribution for the mixer boosts, ADC, front-end mixer, and PGAs can be set in one of four modes. The four ...
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ADAU1381 Register 16398 (0x400E), Record Gain Left PGA The record gain left PGA control register controls the left channel input PGA. This register configures the input for either differ- ential or single-ended signals and sets the left channel input recording ...
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Register 16399 (0x400F), Record Gain Right PGA The record gain right PGA control register controls the right channel input PGA. This register configures the input for either differential or single-ended signals and sets the right channel input recording volume. Bits[7:5], ...
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ADAU1381 Register 16400 (0x4010), Microphone Bias Control and Beep Enable Bit 4, Beep Input Enable This bit enables the beep signal, which is input to the BEEP pin. Setting this bit to 0 mutes the beep signal for all output ...
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SERIAL PORT CONFIGURATION Register 16405 (0x4015), Serial Port Control 0 Bit 5, LRCLK Mode This bit sets the serial port frame clock (LRCLK) as either a 50% duty cycle waveform or a pulse synchronization waveform. When in slave mode, the ...
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ADAU1381 BCLK POLARITY LRCLK BCLK SDATA LRCLK BCLK SDATA LRCLK POLARITY LRCLK LRCLK LRCLK STEREO CHANNELS TDM 4 CHANNELS TDM 8 CHANNELS 1 LRCLK TDM 4 CHANNELS FIRST PAIR 1 TDM 8 CHANNELS Figure 57. Serial Port BCLK Polarity L ...
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Register 16406 (0x4016), Serial Port Control 1 Bits[7:5], Number of Bit Clock Cycles per Frame These bits set the number of BCLK cycles contained in one LRCLK period. The frequency of BCLK is calculated as the number of bit clock ...
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ADAU1381 LRCLK BCLK LRCLK BCLK ...
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LRCLK BCLK SERIAL DATA M (DELAY BY 0) SERIAL DATA M (DELAY BY 1) SERIAL DATA M (DELAY BY 8) LRCLK BCLK ...
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ADAU1381 AUDIO CONVERTER CONFIGURATION Register 16407 (0x4017), Converter Control 0 Bits[6:5], On-Chip DAC Data Selection in TDM Mode These bits set the position of the DAC input channels on a TDM stream. In TDM 4 mode, valid settings are first ...
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LRCLK FIRST PAIR LEFT TDM 4 CHANNELS FIRST PAIR TDM 8 CHANNELS LEFT RIGHT Figure 68. Example of Left Channel First, First Pair TDM Setting LRCLK FIRST PAIR TDM 4 CHANNELS FIRST PAIR TDM 8 CHANNELS Figure 69. Example of ...
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ADAU1381 Register 16408 (0x4018), Converter Control 1 Bits[1:0], On-Chip ADC Data Selection in TDM Mode These bits set the position of the ADC output channels on a TDM stream. In TDM 4 mode, valid settings are first pair or second ...
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Register 16409 (0x4019), ADC Control Bit 6, Invert Input Polarity This bit enables an optional polarity inverter in the ADC path, which is an amplifier with a gain of −1, representing a 180° phase shift. Bit 5, High-Pass Filter Select ...
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ADAU1381 Register 16410 (0x401A), Left ADC Attenuator Bits[7:0], Left ADC Digital Attenuator These bits control a 256-step, logarithmically spaced volume control from −95.625 dB, in increments of 0.375 dB. When a new value is entered into this ...
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PLAYBACK PATH CONFIGURATION Register 16412 (0x401C), Playback Mixer Left Control Bit 5, Left DAC Mute This bit mutes the left DAC output. It does not have any slew and is updated immediately when the register write has been completed. This ...
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ADAU1381 Register 16415 (0x401F), Playback Mono Mixer Control Bit 7, Left DAC Mute This bit mutes the left DAC output, but does not power down the DAC. Use of this bit does not result in power savings. Bit 6, Right ...
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Register 16421 (0x4025), Left Line Output Mute Bit 1, Left Line Output Mute This bit mutes the left line output. It does not have any effect on the speaker outputs. Table 51. Left Line Output Mute Register Bits Description [7:2] ...
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ADAU1381 Register 16423 (0x4027), Playback Speaker Output Control Bits[7:6], Speaker Output Gain Control These bits control the gain of the speaker output. In general, this parameter should be tuned at a system level, set once during system initialization and not ...
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Register 16425 (0x4029), Playback Power Management This register controls the unity current supplied to each functional block described. Within the functional blocks, the current can be multiplied. Normal operation has a base current of 2.5 μA, enhanced performance has a ...
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ADAU1381 Register 16426 (0x402A), DAC Control Bits[7:6], Mono Mode These bits control the output mode of the DAC. Setting these bits to 00 outputs two distinct channels, left and right. Setting these bits to 01 outputs the left input channel ...
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Register 16427 (0x402B), Left DAC Attenuator Bits[7:0], Left DAC Digital Attenuator These bits control a 256-step, logarithmically spaced volume control from −95.625 dB, in increments of 0.375 dB. When a new value is entered into this register, ...
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ADAU1381 PAD CONFIGURATION Figure 71 shows a block diagram of the pad design for the GPIO/serial port and communications port pins. OUTPUT ENABLE OUTPUT PULL-UP ENABLE (CONTROLS PMOS) DEBOUNCE ENABLE DATA IN DEBOUNCE WEAK PULL-UP ENABLE WEAK PULL-DOWN ENABLE DRIVE ...
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Register 16429 (0x402D), Serial Port Pad Control 0 Bits[7:6], ADC_SDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[5:4], DAC_SDATA ...
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ADAU1381 Register 16430 (0x402E), Serial Port Pad Control 1 Bit 3, ADC_SDATA Pin Drive Strength This bit sets the drive strength of the ADC_SDATA pin. Low mode yields 2 mA when IOVDD = 3 0.75 mA when IOVDD ...
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Register 16431 (0x402F), Communication Port Pad Control 0 Bits[7:6], CDATA Pad Pull-Up/Pull-Down These bits enable or disable a weak pull-up or pull-down device on the pad. The effective resistance of the pull-up or pull-down is nominally 240 kΩ. Bits[5:4], CLATCH ...
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ADAU1381 Register 16432 (0x4030), Communication Port Pad Control 1 Bit 3, CDATA Pin Drive Strength This bit sets the drive strength of the CDATA pin. Low mode yields 2 mA when IOVDD = 3 0.75 mA when IOVDD ...
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Register 16433 (0x4031), MCKO Control Bit 2, MCKO Pin Drive Strength This bit sets the drive strength of the MCKO pin. Low mode yields 2 mA when IOVDD = 3 0.75 mA when IOVDD = 1.8 V. High ...
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ADAU1381 Register 16434 (0x4032), Dejitter Control Bits[7:0], Dejitter Window Size The dejitter control register not only allows the size of the dejitter window to be set, but also allows all dejitter circuits in the device to be activated or bypassed. ...
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DIGITAL SUBSYSTEM CONFIGURATION Register 16512 (0x4080), Digital Power-Down 0 Bit 7, ADC Engine Setting this bit to 0 disables the ADCs and the digital micro- phone inputs. Bit 6, Memory Controller Setting this bit to 0 disables all memory access, ...
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ADAU1381 Register 16513 (0x4081), Digital Power-Down 1 Bit 3, Output Precharge The output precharge system allows the outputs to be biased before they are enabled and prevents pops or clicks from appearing on the output. This bit should be set ...
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Register 16582 to Register 16586 (0x40C6 to 0x40CA), GPIO Pin Control Bits[3:0], GPIO Pin Function The GPIO pin control register sets the functionality of each GPIO pin as depicted in Table 68. GPIO0 to GPIO3 use the same pins as ...
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ADAU1381 Register 16617 and Register 16618 (0x40E9 and 0x40EA), Nonmodulo These registers set the boundary for the nonmodulo RAM space used by the sound engine. An appropriate value is automatically loaded to this register during initialization. It should not be ...
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Register 16626 (0x40F2), Serial Input Route Control Bits[3:0], Input Routing These bits select which serial data input channels are routed to the DACs (see Figure 72). Table 72. Serial Input Route Control Register Bits Description [7:4] Reserved [3:0] Input routing ...
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ADAU1381 Register 16627 (0x40F3), Serial Output Route Control Bits[3:0], Output Routing These bits select where the ADC outputs are routed in the serial data stream (see Figure 72). Table 73. Serial Output Route Control Register Bits Description [7:4] Reserved [3:0] ...
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Register 16628 (0x40F4), Serial Data/GPIO Pin Configuration Bits[3:0], GPIO[0:3] The serial data/GPIO pin configuration register controls the functionality of the serial data port pins. If the bits in this register are set to 1, then the GPIO[0:3] pins become GPIO ...
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... TOP VIEW (BALL SIDE DOWN) ORDERING GUIDE 1 Model Temperature Range ADAU1381BCPZ −25°C to +85°C ADAU1381BCPZ-RL −25°C to +85°C ADAU1381BCPZ-RL7 −25°C to +85°C ADAU1381BCBZ-RL −25°C to +85°C ADAU1381BCBZ-RL7 −25°C to +85°C EVAL-ADAU1381Z RoHS Compliant Part. Purchase of licensed I ...