ADAU1381BCPZ Analog Devices Inc, ADAU1381BCPZ Datasheet - Page 49

IC AUDIO CODEC STEREO LN 32LFCSP

ADAU1381BCPZ

Manufacturer Part Number
ADAU1381BCPZ
Description
IC AUDIO CODEC STEREO LN 32LFCSP
Manufacturer
Analog Devices Inc
Type
Stereo Audior
Datasheet

Specifications of ADAU1381BCPZ

Data Interface
Serial, SPI™
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
No
S/n Ratio, Adcs / Dacs (db) Typ
97 / 100
Dynamic Range, Adcs / Dacs (db) Typ
96.5 / 100
Voltage - Supply, Analog
1.8 V ~ 3.65 V
Voltage - Supply, Digital
1.63 V ~ 3.65 V
Operating Temperature
-25°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-VFQFN, CSP Exposed Pad
Audio Codec Type
Stereo
No. Of Adcs
2
No. Of Dacs
2
No. Of Input Channels
3
No. Of Output Channels
3
Adc / Dac Resolution
24bit
Adcs / Dacs Signal To Noise Ratio
100dB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Register 16393 (0x4009), Record Power Management
This register manages the power consumption for the record
path. In particular, the current distribution for the mixer boosts,
ADC, front-end mixer, and PGAs can be set in one of four
modes. The four modes of operation available that affect the
performance of the device are normal operation, power saving,
enhanced performance, and extreme power saving. Normal
operation has a base current of 2.5 μA, enhanced performance
has a base current of 3 μA, power saving has a base current of
a 2 μA, and extreme power saving has a base current of 1.5 μA.
Enhanced performance offers the highest performance, but
with the trade-off of higher power consumption.
Table 36. Record Power Management Register
Bits
7
[6:5]
[4:3]
[2:1]
0
Description
Reserved
Mixer amplifier boost
00: normal operation
01: Boost Level 1
10: Boost Level 2
11: Boost Level 3
ADC bias control
00: normal operation
01: extreme power saving
10: power saving
11: enhanced performance
Front-end bias control
00: normal operation
01: extreme power saving
10: power saving
11: enhanced performance
Reserved
Rev. B | Page 49 of 84
Bits[6:5], Mixer Amplifier Boost
These bits set the power mode of operation for the front-end
mixer boost. With higher AVDD1 levels, distortion may become
an issue affecting performance. Each boost level enhances the
THD + N performance at 3.3 V AVDD1.
Bits[4:3], ADC Bias Control
These bits set the bias current for the ADCs based on the mode
of operation selected.
Bits[2:1], Front-End Bias Control
These bits set the bias current for the PGAs and mixers in the
front-end record path.
Default
00
00
00
ADAU1381

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