ADAU1381BCPZ Analog Devices Inc, ADAU1381BCPZ Datasheet - Page 11

• Manufacturer Part Number: ADAU1381BCPZ
• Description: IC AUDIO CODEC STEREO LN 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Stereo Audior

Specifications of ADAU1381BCPZ

• Data Interface: Serial, SPI™
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 97 / 100
• Dynamic Range, Adcs / Dacs (db) Typ: 96.5 / 100
• Voltage - Supply, Analog: 1.8 V ~ 3.65 V
• Voltage - Supply, Digital: 1.63 V ~ 3.65 V
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 3
• No. Of Output Channels: 3
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 100dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DIGITAL TIMING SPECIFICATIONS
−25°C < T
Table 7. Digital Timing
Parameter
MASTER CLOCK
SERIAL PORT
SPI PORT
I
DIGITAL MICROPHONE
2
C PORT
t
Duty Cycle
t
t
t
t
t
t
t
f
f
f
f
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CCLK,R
CCLK,R
CCLK,W
CCLK,W
SCL
MP
BIL
BIH
LIS
LIH
SIS
SIH
SODM
CCPL
CCPH
CLS
CLH
CLPH
CDS
CDH
COD
SCLH
SCLL
SCS
SCH
DS
SCR
SCF
SDR
SDF
BFT
DCF
DCR
DDV
DDH
A
< +85°C, IOVDD = 1.62 V to 3.63 V, unless otherwise specified.
t
50
30
10
10
5
5
5
5
10
10
10
5
10
5
5
0.6
1.3
0.6
0.6
100
0.6
22
0
MIN
Limit
t
90.9
70
70
5
10
25
25
70
40
400
300
300
300
300
10
10
30
12
MAX
Unit
ns
%
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
μs
ns
ns
ns
ns
Rev. B | Page 11 of 84
Description
Master clock (MCLK) period (that is, period of the signal input to MCKI).
BCLK pulse width low.
BCLK pulse width high.
LRCLK setup. Time to BCLK rising.
LRCLK hold. Time from BCLK rising.
DAC_SDATA setup. Time to BCLK rising.
DAC_SDATA hold. Time from BCLK rising.
ADC_SDATA delay. Time from BCLK falling in master mode.
CCLK frequency, read operation, IOVDD = 1.8 V ± 10%.
CCLK frequency, read operation, IOVDD = 3.3 V ± 10%.
CCLK frequency, write operation, IOVDD = 1.8 V ± 10%.
CCLK frequency, write operation, IOVDD = 3.3 V ± 10%.
CCLK pulse width low.
CCLK pulse width high.
CLATCH setup. Time to CCLK rising.
CLATCH hold. Time from CCLK rising.
CLATCH pulse width high.
CDATA setup. Time to CCLK rising.
CDATA hold. Time from CCLK rising.
COUT delay from CCLK edge to valid data, IOVDD = 1.8 V ± 10%.
COUT delay from CCLK edge to valid data, IOVDD = 3.3 V ± 10%.
SCL frequency.
SCL high.
SCL low.
Setup time; relevant for repeated start condition.
Hold time. After this period, the first clock is generated.
Data setup time.
SCL rise time.
SCL fall time.
SDA rise time.
SDA fall time.
Bus-free time. Time between stop and start.
R
Digital microphone clock fall time.
Digital microphone clock rise time.
Digital microphone delay time for valid data.
Digital microphone delay time for data three-stated.
L
= 1 MΩ, C
L
= 14 pF.
ADAU1381