EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 81

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

UART Recommended Usage
PS006614-1208
UART Modem Status Interrupt
Module Reset
Control Transfers
A line status interrupt is activated (provided this interrupt is enabled) as long as the read
pointer of the receive FIFO points to the location of the FIFO that contains a byte with the
error. The interrupt is immediately cleared when the UARTx_LSR register is read. The
ERR bit of the UARTx_LSR register is active as long as an error byte is present in the
receive FIFO.
The modem status interrupt is generated if there is any change in state of the modem status
inputs to the UART. This interrupt is cleared when the processor reads the UARTx_MSR
register.
The following is the standard sequence of events that occurs in the eZ80190 device using
the UART. A description of each follows.
•
•
•
Upon reset, all internal registers return to their default values. All command status regis-
ters are programmed with their default values and the FIFOs are flushed.
Based on the application requirement, the data transfer baud rate is determined and the
BRG is configured to generate a 16X clock frequency, provided at the BRG signal input.
Interrupts are disabled and communication control parameters are programmed in the
UARTx_LCTL register. The FIFO configuration is determined and the receive trigger lev-
els are set in the UARTx_FCTL register. The status registers, UARTx_LSR and
UARTx_MSR, are read to ensure that no interrupt sources are active. Interrupts are
enabled (except for the transmit interrupt) and the application is ready to use the module
for transmission and reception.
Module reset
Control transfers to configure UART operation
Data transfers
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80190
71