EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 50

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

WDT Operation
WDT Registers
PS006614-1208
Enabling And Disabling The WDT
Time-Out Period Selection
RESET Or NMI Generation
WDT Control Register
The WDT is disabled upon a system RESET. To enable the WDT, the application program
must set the WDT_EN bit (bit 7) of the WDT_CTL register. When enabled, the WDT can-
not be disabled without a system RESET.
There are four choices of time-out periods for the WDT—2
clock cycles. With a 50 MHz crystal oscillator, the available WDT time-out periods are
approximately 5.24 ms, 83.9 ms, 671 ms, and 2.68 s. The WDT time-out period is defined
by the WDT_PERIOD field of the WDT_CTL register (WDT_CTL[1:0]).
Upon a WDT time-out, the RST_FLAG bit in the WDT_CTL register is set to 1. In addi-
tion, the WDT can cause a system RESET or send a nonmaskable interrupt (NMI) signal
to the CPU. The default operation is for the WDT to cause a system RESET. The reset
pulse generated by a WDT time-out is 64 clock cycles wide. It asserts/deasserts on the ris-
ing edge of the clock. The RST_FLAG bit can be polled by the CPU to determine the
source of the RESET event.
If the NMI_OUT bit in the WDT_CTL register is set to 1, then upon time-out, the WDT
asserts an NMI for CPU processing. The RST_FLAG bit can be polled by the CPU to
determine the source of the NMI event.
The WDT Control register, listed in
used to enable the WDT, set the time-out period, indicate the source of the most recent
RESET, and select the required operation upon WDT time-out.
Table 10
on page 41, is an 8-bit Read/Write register
18
, 2
22
Product Specification
, 2
25
, and 2
Watchdog Timer
27
system
eZ80190
40