EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 117

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

PS006614-1208
When the Bus Enable bit (ENAB) is set to 0, the I
and the I
the I
(I2Cx_SAR[0]) is set to 1.
When the MASTER Mode Start bit (STA) is set to 1, the I
sends a START condition on the bus when the bus is free. If the STA bit is set to 1 when
the I
repeated START condition is sent. If the STA bit is set to 1 when the I
accessed in SLAVE mode, the I
enters MASTER mode when the bus is released. The STA bit is automatically cleared after
a START condition is set. Writing a 0 to this bit produces no effect.
If the MASTER Mode Stop bit (STP) is set to 1 in MASTER mode, a STOP condition is
transmitted on the I
behaves as if a STOP condition is received, but no STOP condition is transmitted. If both
STA and STP bits are set, the I
mode) and then transmits the START condition. The STP bit is cleared automatically.
Writing a 0 to this bit produces no effect.
The I
the possible 31 I
IFLG is set to 1 and the IEN bit is also set to 1, an interrupt is generated. When IFLG is set
by the I
suspended. When a 0 is written to IFLG, the interrupt is cleared and the I
released.
When the I
Acknowledge clock pulse on the I
•
•
•
When ACK is cleared to 0, a NACK is sent when a data byte is received in MASTER or
SLAVE mode. If ACK is cleared to 0 in SLAVE TRANSMIT mode, the byte in the
I2Cx_DR register is presumed to be the last byte. After this byte is transmitted, the I
block enters state
its slave address unless ACK is set.
Either the whole of a 7-bit slave address or the first or second byte of a 10-bit slave
address is received
The general call address is received and the General Call Enable bit in I2Cx_SAR is
set to 1
A data byte is received in MASTER or SLAVE mode
2
2
2
C responds to calls to its slave address and to the general call address if the GCE bit
C module is already in MASTER mode and one or more bytes are transmitted, then a
C Interrupt Flag (IFLG) is set to 1 automatically when the device enters any of 30 of
2
2
C, the Low period of the I
C module does not respond to any address on the bus. When ENAB is set to 1,
2
C Acknowledge bit (ACK) is set to 1, an acknowledgement is sent during the
2
C states. The only state that does not set the IFLG bit is state
C8h
2
C bus. If the STP bit is set to 1 in SLAVE mode, the I
, then returns to the IDLE state. The I
2
C block first transmits the STOP condition (if in MASTER
2
C completes the data transfer in SLAVE mode and then
2
2
C bus if:
C bus clock line is stretched and the data transfer is
2
C bus inputs SCLx. SDAx is ignored
2
2
C enters MASTER mode and
C module does not respond to
Product Specification
I2C Serial I/O Interface
2
C block is being
2
C clock line is
2
C module
F8h
. If
2
C
107