EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 133

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

PS006614-1208
OUT_SHIFT Function
The OUT_SHIFT field, bits 5:3 of the MACC_CTL register, defines the magnitude of the
right-shift that is performed when the CPU reads a result from the MACC Accumulator
registers MACC_AC0, MACC_AC1, MACC_AC2, MACC_AC3, and MACC_AC4. The
MACC automatically manipulates the shift of the 40-bit value as it is read as a succession
of 8-bit values. The READs can be right-shifted 0 to 7 bits depending upon the value of
OUT_SHIFT. Because the MACC Accumulator value is a two’s-complement value, the
upper bits are filled with copies of the sign bit, bit 39, during the right-shift operation.
Example 1—
are not shifted. If the 40-bit MACC Accumulator value is read using a succession of 8-bit
READs, the procedure appears as follows:
1. Read the LSB from the MACC Accumulator
2. Read the second byte from the MACC Accumulator
3. Read the third byte from the MACC Accumulator
4. Read the fourth byte from the MACC Accumulator
5. Read the MSB from the MACC Accumulator
Example 2—
are right-shifted by 3 bits. The 3 msbs are filled with copies of the msb of the 40-bit
MACC Accumulator. In this example, assume the MACC Accumulator currently contains
a positive number so that the msb is 0. If the 40-bit MACC Accumulator value is read
using a succession of 8-bit reads, the procedure appears as follows:
1. Read the LSB from the MACC Accumulator
2. Read the second byte from the MACC Accumulator
3. Read the third byte from the MACC Accumulator
DATA_OUT[7:0] = MACC_AC0[7:0] = MACC Accumulator [7:0]
DATA_OUT[7:0] = MACC_AC1[7:0] = MACC Accumulator [15:8]
DATA_OUT[7:0] = MACC_AC2[7:0] = MACC Accumulator [23:16]
DATA_OUT[7:0] = MACC_AC2[7:0] = MACC Accumulator [31:24]
DATA_OUT[7:0] = MACC_AC2[7:0] = MACC Accumulator [39:32]
DATA_OUT[7:0] = MACC_AC0[7:0] = MACC Accumulator [10:3]
DATA_OUT[7:0] = MACC_AC1[7:0] = MACC Accumulator [18:11]
DATA_OUT[7:0] = MACC_AC2[7:0] = MACC Accumulator [26:19]
When OUT_SHIFT =
When OUT_SHIFT =
011b
000b
, READs from the MACC Accumulator registers
, reads from the MACC Accumulator registers
Product Specification
Multiply-Accumulator
eZ80190
123