EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 74

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

UZI and BRG Control Registers
PS006614-1208
UZI Control Registers
Table 23. UZI Control Registers
BRG Divisor Latch Registers—Low Byte
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
[7:2]
[1:0]
UZI_MODE
•
The UZI Control registers select between the three available serial communication con-
trollers: I
its own UZI Control register.
This register holds the Low byte of the 16-bit divisor count loaded by the processor for
baud rate generation. The 16-bit clock divisor value is returned by {BRGx_DLR_H,
BRGx_DLR_L}, where x is either 0 or 1 to identify the two available UZI devices. Upon
RESET, the 16-bit BRG divisor value resets to
must be between
proper operation is not guaranteed. Thus the minimum BRG clock divisor ratio is 2.
A write to either the Low or High byte registers for the BRG Divisor Latch causes both
bytes to be loaded into the BRG counter and the count restarted.
Bit 7 of the associated UART Line Control register (UARTx_LCTL) must be set to 1 to
access this register for each UZI device. For more information see
Register
Clear UARTx_LCTL[7] to 0 to disable access of the BRG divisor registers.
Value
000000 Reserved
00
01
10
11
on page 77 (UARTx_LCTL).
2
C, SPI and UART. Each of the two UZI devices on the eZ80190 device features
0002h
Description
All UZI devices are disabled.
UART is enabled.
SPI is enabled.
I
2
R
7
0
C is enabled.
and
R
6
0
FFFFh
R
5
0
as the values
(UZI0_CTL = CFh, UZI1_CTL = DFh)
R
4
0
0002h
0000h
R
3
0
. The initial 16-bit divisor value
and
R
2
0
0001h
Product Specification
UART Line Control
R/W
Universal Zilog Interface
1
0
are invalid and
R/W
0
0
eZ80190
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