EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 107

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

Operating Modes
PS006614-1208
Clock Synchronization for Handshake
Master Transmit
In other words, arbitration is not allowed between:
•
•
•
The Clock synchronizing mechanism can function as a handshake, enabling receivers to
cope with fast data transfers, on either a byte or bit level. The byte level allows a device to
receive a byte of data at a fast rate, but allows the device more time to store the received
byte or to prepare another byte for transmission. Slaves hold the SCL line Low after recep-
tion and acknowledge the byte, forcing the master into a WAIT state until the slave is
ready for the next byte transfer in a handshake procedure.
In MASTER TRANSMIT mode, the I
The device enters MASTER TRANSMIT mode by setting the Master Mode Start bit
(STA) bit in the I2Cx_CTL register to 1. The I
START condition when the bus is free. When a START condition is transmitted, the IFLG
bit is set to 1 and the status code in the I2Cx_SR register is
serviced, the I2Cx_DR register must be loaded with either a 7-bit slave address or the first
part of a 10-bit slave address, with the lsb cleared to 0 to specify TRANSMIT mode. The
IFLG bit should now be cleared to 0 to prompt the transfer to continue.
After the 7-bit slave address (or the first part of a 10-bit address) plus the write bit are
transmitted, the IFLG is set again. A number of status codes are possible in the I2Cx_SR
register.
A repeated START condition and a data bit
A STOP condition and a data bit
A repeated START condition and a STOP condition
2
C transmits a number of bytes to a slave receiver.
2
C then tests the I
08h
. Before this interrupt is
2
Product Specification
C bus and transmits a
I2C Serial I/O Interface
97