EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 78

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

UART Functional Description
UART Functions
PS006614-1208
UART Transmitter
The core uses an externally-provided clock from the Baud Rate Generator for the serial
transmit/receive function. The UART module supports all of the various options in the
asynchronous transmission and reception protocol including:
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The UART contains 16-byte FIFOs in each direction. The FIFOs can be enabled or dis-
abled by the application. The receive FIFO features trigger-level detection logic, which
enables the processor to block transfer data bytes from the receive FIFO.
The UART data transfer rate is calculated in the following equation:
The UART function implements:
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The transmitter block controls the data transmitted on the TXD output. It implements the
FIFO, accessed through the UARTx_THR register, the transmit shift register, the parity
generator, and control logic for the transmitter to control parameters for the asynchronous
communications protocol.
The UARTx_THR is a Write Only register. The processor writes the data byte to be trans-
mitted into this register. In FIFO mode, up to 16 data bytes can be written through the
UARTx_THR register. The data byte from the FIFO is transferred to the transmit shift reg-
ister and transmitted on the TXD pin. After SYNC_RESET, the UARTx_THR register is
empty so the Transmit Holding Register Empty (THRE) bit (bit 5 of the UARTx_LSR reg-
UART Data Transfer Rate (bits/s) =
5 to 8-bit transmit/receive
Start bit generation and detection
Parity generation and detection
Stop bit generation and detection
Break generation and detection
The transmitter and associated control logic
The receiver and associated control logic
The modem interface and associated logic
16 x Baud Rate Generator Divisor
System Clock Frequency
Universal Asynchronous Receiver/Transmitter
Product Specification
eZ80190
68