EZ80190AZ050SG Zilog, EZ80190AZ050SG Datasheet - Page 110

• Manufacturer Part Number: EZ80190AZ050SG
• Description: IC WEBSERVER 8 BIT 50MHZ 100LQFP
• Manufacturer: Zilog

Specifications of EZ80190AZ050SG

• Processor Type: eZ80
• Features: High Speed, Single-Cycle Instruction-Fetch
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Processor Series: EZ80190x
• Core: eZ80
• Data Bus Width: 8 bit
• Program Memory Type: ROMLess
• Data Ram Size: 8 KB
• Interface Type: I2C, IrDA, SPI, UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 6
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3866; EZ80190AZ050SG

Table 45. I
PS006614-1208
Code
28h
30h
38h
Master Receive
Data byte transmitted, ACK
Data byte transmitted, ACK not
Arbitration lost
I
received
received
2
C State
2
C Master Transmit Status Codes For Data Bytes
When all bytes are transmitted, the microprocessor should write a 1 to the Master Mode
Stop bit (STP) bit in the I2Cx_CTL register. The I
clears the STP bit, and returns to the IDLE state.
In MASTER RECEIVE mode, the I
ter.
After the START condition is transmitted, the IFLG bit is set to 1 and the status code
is loaded in the I2Cx_SR register. The I2Cx_DR register should be loaded with the slave
address (or the first part of a 10-bit slave address), with the lsb set to 1 to signify a READ.
The IFLG bit should be cleared to 0 as a prompt for the transfer to continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the read bit are
transmitted, the IFLG bit is set and one of the status codes listed in
contained in the I2Cx_SR register.
Microprocessor Response
Write byte to DATA, clear IFLG Transmit data byte,
Or set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP, clear IFLG
Same as code 28h
Clear IFLG
Or set STA, clear IFLG
2
C receives a number of bytes from a slave transmit-
2
C then transmits a STOP condition,
Next I
receive ACK
Transmit repeated
START
Transmit STOP
Transmit START then
STOP
Same as code 28h
Return to the IDLE state
Transmit START when
bus free
Product Specification
Table 46
2
C Action
I2C Serial I/O Interface
on page 101 is
08h
100