MAX1403EAI+ Maxim Integrated Products, MAX1403EAI+ Datasheet - Page 7

• Manufacturer Part Number: MAX1403EAI+
• Description: IC ADC 18BIT LP 28-SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1403EAI+

• Number Of Bits: 18
• Sampling Rate (per Second): 480
• Data Interface: QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 21.45mW
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SSOP
• Number Of Adc Inputs: 5
• Architecture: Delta-Sigma
• Conversion Rate: 4.8 KSPs
• Resolution: 18 bit
• Input Type: Voltage
• Interface Type: Serial
• Voltage Reference: External
• Supply Voltage (max): 3 V
• Maximum Power Dissipation: 21.45 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Input Signal Type: Pseudo-Differential, Differential
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TIMING CHARACTERISTICS
(V+ = +2.7V to +3.6V, V
T
Note 16: The burn-out currents require a 500mV overhead between the analog input voltage and both V+ and AGND to operate
Note 17: Measured at DC in the selected passband. PSR at 50Hz will exceed 120dB with filter notches of 25Hz or 50Hz and FAST
Note 18: PSR depends on gain. For a gain of +1V/V, PSR is 70dB typical. For a gain of +2V/V, PSR is 75dB typical. For a gain of
Note 19: Standby power-dissipation and current specifications are valid only with CLKIN driven by an external clock and with the
SERIAL-INTERFACE READ OPERATION
MAX
SERIAL-INTERFACE WRITE OPERATION
Master Clock Frequency
Master Clock Input Low Time
Master Clock Input High Time
INT High Time
RESET Pulse Width Low
INT to CS Setup Time (Note 9)
SCLK Setup to Falling Edge CS
CS Falling Edge to SCLK Falling
Edge Setup Time
SCLK Falling Edge to Data Valid
Delay (Notes 25, 26)
SCLK High Pulse Width
SCLK Low Pulse Width
CS Rising Edge to SCLK Rising
Edge Hold Time (Note 22)
Bus Relinquish Time After SCLK
Rising Edge (Note 27)
SCLK Rising Edge to INT High
(Note 28)
SCLK Setup to Falling Edge CS
, unless otherwise noted.) (Notes 20, 21, 22)
correctly.
PARAMETER
bit = 0. PSR at 60Hz will exceed 120dB with filter notches of 20Hz or 60Hz and FAST bit = 0.
+4V/V, PSR is 80dB typical. For gains of +8V/V to +128V/V, PSR is 85dB typical.
external clock stopped. If the clock continues to run in standby mode, the power dissipation will be considerably higher.
When used with a resonator or crystal between CLKIN and CLKOUT, the actual power dissipation and I
mode will depend on the resonator or crystal type.
_______________________________________________________________________________________
DD
= +2.7V to +3.6V, AGND = DGND, f
+3V, 18-Bit, Low-Power, Multichannel,
SYMBOL
f
f
CLKIN LO
CLKIN HI
f
CLKIN
t
t
t
t
INT
t
t
t
t
t
t
t
t
10
11
12
2
3
4
5
6
7
8
9
Oversampling (Sigma-Delta) ADC
Crystal oscillator or clock exter-
nally supplied for specified perfor-
mance (Notes 23, 24)
t
t
X2CLK = 0, N = 2
X2CLK = 1, N = 2
CLKIN
CLKIN
= 1 / f
= 1 / f
CLKIN
CLKIN
CONDITIONS
CLKIN
(2
(2
, X2CLK = 0
, X2CLK = 0
·
·
MF1 + MF0)
MF1 + MF0)
= 2.4576MHz, input logic 0 = 0V, logic 1 = V
X2CLK = 0
X2CLK = 1
·
·
280 / N
560 / N
t
t
CLKIN
CLKIN
t
t
0.4
0.4
MIN
CLKIN
100
100
100
CLKIN
0.4
0.8
30
30
10
30
0
0
0
0
·
·
TYP
DD
DD
MAX
in standby
100
100
100
200
2.5
5.0
, T
A
= T
UNITS
MHz
MIN
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
to
7