EW80314GN S L8AZ Intel, EW80314GN S L8AZ Datasheet - Page 9

• Manufacturer Part Number: EW80314GN S L8AZ
• Manufacturer: Intel

Specifications of EW80314GN S L8AZ

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Errata (Sheet 1 of 2)
Intel
®
80314 I/O Processor Companion Chip Specification Update
No.
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A-0
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Steppings
B-0
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B-1
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Status
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
No Fix
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
Fixed
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Fixed
PE_CSR[R_TA] status bit may not be set
Large burst read may result in SFN queue overwrite
TX FIFO may be mismanaged in half-duplex mode
Frame abort feature does not work
CLK_EN signal may glitch high
High DC current draw when core supply collapses
LS_VECTOR field of the VECTORx registers may report
incorrect value 0
A VECTORx read of 0xFF does not always mean that no
interrupts are pending
Two Intel XScale® cores cannot be the target of a single
interrupt
DMA channel may require reset following SFN TEA errors
Limitations on SFN outstanding transactions
DMA and CRC32 or byte-swapping and CRC32 in a single
operation may corrupt data
RxQueue INT is not triggered on error condition
Blank EPROM delays booting of the Intel® 80314 I/O
Processor Companion Chip
Inconsistent results when using SRAM
Multi-byte writes are not supported on the Intel® 80314 I/O
Processor Companion Chip
Register swapping lock up
Enable Relaxed Ordering Bit attributes
Bus master enable bit not functional
Remaining byte-count in split completion message may be
incorrect
SDRAM bridging throughput performance limitations
Extra clock cycle on SRAM reads
Use of MSI
IRP_INTAD must be used to mask PCI INTs
MemRead DWORD transaction writes to reserved bits
PFAB_CSR TEA bit is not functional
Bus Number is not updated correctly in the PCI-X Status
Register
PCIXCAP[1:0] = 01b is not a valid setting
Clock synchronization issues
DMA channel hangs when it is stopped with STOP_REQ
while CRC is enabled
Summary Table of Changes
Errata
9