EW80314GN S L8AZ Intel, EW80314GN S L8AZ Datasheet - Page 24

• Manufacturer Part Number: EW80314GN S L8AZ
• Manufacturer: Intel

Specifications of EW80314GN S L8AZ

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Errata
35.
Problem:
Implication:
Workaround:
Status:
36.
Problem:
Implication:
Workaround:
Status:
37.
Problem:
Implication:
Workaround:
Status:
24
Erroneous “undersize frame counter” increment
A Gigabit Ethernet under-run may result in an erroneous “undersize frame counter” increment.
Under heavy SFN traffic, the MAC may empty the TX FIFO faster than it is able to be fed by the
DMA/SFN. As a result, the transceiver is not kept busy, and a TX error condition is triggered
(under-run). When an under-run occurs, the MAC deliberately sends a bad CRC to force the
receiver to discard the packet, but the “CRC error bit” is not set and the frame size is zeroed. This
causes the statistics unit to erroneously detect an “undersized frame” (0 bytes) with a good
CRC(FSC). As a result, the TUND (Transmit Undersize) Frame Counter field of PE-MSTAT
(Table 296) of the MAC increments (address F8/4F8).
The transmit undersize frame counter statistics counter is off by number of transmit under-run
events that have occurred.
During heavy traffic conditions, any TX frame larger than 2K may under-run, including jumbo
frames.
Occurrence of under-run is highly dependent on the application and data profile; many applications
do not experience this error.
To avoid under-run during heavy traffic conditions:
Some applications can use frames larger than 2K without occurrence of over-run and incorrect
incrementing of TUND.
No Fix
I
I
I
Follow single-byte read time-outs with a single-byte read to a valid device.
No Fix
Incorrect PME output signaling
PME pin signaling is implemented incorrectly such that P1_PME# and P2_PME# signals are
incorrectly driven high in the active state. These pins must be open-drain bi-directional such that
they are three-state inactive (pulled high by external pull-up) and driven low (active).
P1_PME# and P2_PME# signals cannot be driven low (active) and instead drive high (active).
None
Fixed
2
2
2
1. Use only frame sizes <= 2K, so they can be entirely buffered in TX FIFO.
2. Ensure entire frame is buffered in FIFO prior to the start of transmission by setting the “Start
C can lock up when a multi-byte read follows a time-out from a single-byte read.
C hangs. The 80314 must be reset.
C hang condition
sending threshold” TX Thresholds register (Offset: 0x230/0x630) >= the frame size. See
Table 376 of the Intel
Intel
®
®
80314 I/O Processor Companion Chip Developer’s Manual.
80314 I/O Processor Companion Chip Specification Update