EW80314GN S L8AZ Intel, EW80314GN S L8AZ Datasheet - Page 34

• Manufacturer Part Number: EW80314GN S L8AZ
• Manufacturer: Intel

Specifications of EW80314GN S L8AZ

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Specification Clarifications
11.
Issue:
Affected Docs: Intel
12.
Issue:
Affected Docs: Intel
13.
Issue:
Affected Docs: Intel
34
Proper handling of multi-bit ECC errors in abort handler
Incorrect handling of multi-bit ECC errors within the abort handler, for 64-bit read accesses to un-
cacheable/un-bufferable memory, can result in multiple data aborts and an invalid link register
leading to CPU crash. For this type of access, the Intel
When multi-bit ECC errors occur, two back-to-back ECC syndromes are presented to the Intel
XScale
To detect this condition and handle it properly, the abort handler must check to see whether the link
register contains 0x14 or points elsewhere. When the link register points to 0x14, this indicates that
the back-to-back abort condition has been triggered. When it points elsewhere, this condition is not
triggered.
For the most up-to-date workaround information, refer to errata #2, “Multiple ECC errors reported
on a single transaction” in the Intel
Specification Update (document number 273415).
Enabling ECC/parity for SRAM
When the proper SRAM initialization sequence is not followed when enabling ECC and parity,
multi-bit ECC errors and parity errors are generated. This can occur when writing 4-byte words
because the CIU unit does a read-modify-write. During the read, the CIU checks the SRAM
content against parity that has not yet been initialized, and thus reports an error.
The proper sequence is as follows:
64-bit PCI/X addressability
Current documentation leads the reader to believe that the PFAB_BAR’s must be enabled for all
SFN PCI/X traffic and are therefore restricted to 5 GB of addressability (PFAB_MEM32 1 G +
PFAB_PFM3 2 G + PFAB_PFM4 2 G).
An outbound SFN transaction routed to a PCI/X port that is not claimed by a PFABx BAR is
passed through untranslated. Thus, where address translation is not required, 64 bits of PCI/X
addressability is available through port routing. This provides 64-bit PCI/X addressability to SFN
sources such as the CIU and DMA. One implication is that the DMA destination port can
conveniently be used to direct DMA to PCI/X transfers to PCI1 or PCI2 memory space.
It is important to remember that PCI/X memory access directly from the Intel XScale
(without DMA/XOR, 32-bit addresses) still needs a configured CIU BAR (and its LUT) to route
the access through to the desired PCI/X port with the correct translated address.
1. Write 0x4 to CIU_CFG register (offset 0x38) to enable parity.
2. Write to every 4-byte word in SRAM—expect a parity error in CIU_ERROR (offset 0x48)
3. Write 0x20 to the CIU_ERROR register to clear the parity error.
®
®
®
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
®
bus, resulting in two aborts and triggering an existing Intel
Intel
®
80314 I/O Processor Companion Chip Specification Update
®
80200 Processor based on Intel XScale
®
80200 issues two 32-bit RMW cycles.
®
80200 errata.
®
Microarchitecture
®
processor