EW80314GN S L8AZ Intel, EW80314GN S L8AZ Datasheet - Page 36

• Manufacturer Part Number: EW80314GN S L8AZ
• Manufacturer: Intel

Specifications of EW80314GN S L8AZ

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Specification Clarifications
18.
Issue:
Affected Docs: Intel
36
PCI Target Abort when Start Address + Cache Line exceeds physical
memory
When the PCI interface is the target of a “Memory Read Multiple” (MRM) command from a bus
master, target aborts can occur when the start address plus the cache-line size exceeds the end of
physical memory. This can occur when the bus master is attempting to read the last few words of
memory. The memory controller fetches cacheline-sized chunks of memory from the memory
controller. A fetch near to the end, but within valid physical memory, can cause a portion of the
fetched chunk to be requested beyond physical memory. When this happens, the PCI interface
signals Target Abort.
This behavior can be avoided by reserving the last page of physical RAM for uses other than PCI
DMA. Some OS implementations simply set the OS managed memory size to one less than the
maximum memory discovered.
This behavior does not apply to operation in PCI-X mode.
Host address map / BAR settings for the Intel
embedded HBA configuration must not hit the end of physical memory. Inbound transactions are
expected to be comprised of mainly command and status operations, with host data transfers being
handled through the internal DMA of the Intel
®
80314 I/O Processor Companion Chip Developer’s Manual
Intel
®
80314 I/O Processor Companion Chip Specification Update
®
®
80314 I/O Processor Companion Chip in the
80314 I/O Processor Companion Chip.