EW80314GN S L8AZ Intel, EW80314GN S L8AZ Datasheet - Page 12

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EW80314GN S L8AZ

Manufacturer Part Number
EW80314GN S L8AZ
Description
Manufacturer
Intel
Datasheet

Specifications of EW80314GN S L8AZ

Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Summary Table of Changes
Specification Clarifications
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®
80314 I/O Processor Companion Chip Specification Update
Byte swapping must be on data word-aligned boundaries
MISC_CSR register SOFT_RESET not only asserts the Px_RST pin but
also resets the PCI block
SD_BANK_CTRL register programming restrictions
Multi-bit ECC error behaviors
Requirements for booting to other than an 8-bit PBI width
Time-outs may result in data overwrites
The Intel® 80314 I/O Processor Companion Chip configuration retry
mechanism requires the use of SEEROM
Intel® 80314 I/O Processor Companion Chip is capable of up to 12 GB but
tested only to 3 GB
Maximum I2C memory
Proper handling of Gigabit Ethernet WAIT condition
Proper handling of multi-bit ECC errors in abort handler
Enabling ECC/parity for SRAM
64-bit PCI/X addressability
Reset of Intel® 80314 I/O Processor Companion Chip primary PCI/X
without host PCI/X reset
PCI/X cannot be the destination of a sync packet
SRAM enable/disable pin
Driver consideration for shared memory structures under PORT_ARB = 01
PCI Target Abort when Start Address + Cache Line exceeds physical
memory
Specification Clarifications

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