EW80314GN S L8AZ Intel, EW80314GN S L8AZ Datasheet - Page 16

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EW80314GN S L8AZ

Manufacturer Part Number
EW80314GN S L8AZ
Description
Manufacturer
Intel
Datasheet

Specifications of EW80314GN S L8AZ

Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
Errata
Errata
1.
Problem:
Implication:
Workaround:
Status:
2.
Problem:
Implication:
Workaround:
Status:
3.
Problem:
Implication:
Workaround:
Status:
16
PE_CSR[R_TA] status bit may not be set
When the Intel
configured for embedded mode and the destination is one of the PCI-X interfaces, when the 80314
masters a Mem_Read_Mult command for which it receives target abort, the PE_CSR[R_TA] status
bit is not set.
This behavior prevents the assertion of an interrupt that may be mapped to this bit.
When the source is one of the PCI interfaces, the 80314 signals a target abort to the originating
master.
When the source is one of the PCI-X interfaces, the 80314 returns a split completion message
indicating a device-specific error. When the initiator receives one of these error indications and
finds no status detailing the source of the error after interrogating the PE_CSR register, then the
initiator must interrogate the CSR register of the destination targets to determine whether one of
them signaled a target abort.
All other sources other than the PCI-X blocks receive an SFN response indicating an error.
Fixed
Large burst read may result in SFN queue overwrite
When the 80314 PCI-X interface accepts a burst read that is decomposed (broken down to 256-
byte chunks) for SFN transmission, and an error response is received from the SFN while doing the
completion, then the 80314 overwrites the SFN queue.
This may or may not overwrite the data for the related transaction, and it may also cause issues
with other PCI-X transactions.
Sources of the error can be a Master Abort, Target Abort, PERR, SERR on the other PCI-X port, or
a parity error on the SDRAM interface. When the system sees any of these errors, it must address
the problem and reset the system.
Fixed
TX FIFO may be mismanaged in half-duplex mode
When operating in half-duplex mode, it is possible for the TX FIFO to be mismanaged.
Mismanagement of the TX FIFO may result in under-run reporting and dropped frames. Ultimately
this may lead to a lockup condition in which TX data is no longer transmitted.
Use only full-duplex mode.
Fixed
®
80314 I/O Processor Companion Chip (called hereafter “the 80314”) is
Intel
®
80314 I/O Processor Companion Chip Specification Update

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