EW80314GN S L8AZ Intel, EW80314GN S L8AZ Datasheet - Page 42

• Manufacturer Part Number: EW80314GN S L8AZ
• Manufacturer: Intel

Specifications of EW80314GN S L8AZ

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Documentation Changes
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SDRAM PLL bypass
The “Description” column for SD_I2C_SDA (Table 5) incorrectly states that it can be used to enter
“SDRAM PLL Bypass Mode”. Only the XS__FIQ[1]/PWRUP_SD_BYP pin can enter SDRAM
PLL bypass mode.
PWRDELAY circuitry not required for non-battery-backup designs
Section 7.5.3 of the Intel
that applications that do not use battery backup still need to implement the PWRDELAY circuitry.
When no battery backup is required, the PWRDELAY pin can be tied to ground.
Design guideline table missing data
Table 14 of the embedded 100 MHz design guidelines is missing lengths (listed as N/A) for the
upper AD bus bits for the W4 and W5 segments. The W4 and W5 segments for the upper address
lines have a minimum length of 1.65" and a maximum length of 3.5".
GPIO attribute reversal
Table 458 of the Intel
reverses the attributes for bits[15:8] and bits[31:24] of the GPIO_DATA register (0x5A0). The
correct attributes for bits[15:8] are RW, and the correct attributes for bits[31:24] are RO.
Single Data Rate SDRAM is not supported
The Intel
80314 memory controller supports Single (SDR) and Double Data Rate (DDR) SDRAM. DDR
SDRAM is supported; SDR is not supported.
EE_Bx_ADDR Register Bit [31:8] description is not correct
The Intel
EE_Bx_ADDR Register bit [31:8] description in Section 7.7.1 as A[31:12]. The correct description
is A[35:12]
Section 2.3.1.3 and 2.3.1.4 not correct
For Sections 2.3.1.3 and 2.3.1.4, the titles are reversed and are incorrect. The new section titles
appear as follows:
2.3.1.3 Scenario S3: Internal DMA (Any Source, Any Destination)
For all scenarios involving internal DMA engines, the interrupt is not raised until the data has been
enqueued to the SFN fabric. This means that the only requirement is to ensure that the data from
the DMA transaction has been flushed from the receiving port’s queue. Sync packets are not used
in this scenario. For example, if internal DMA is used to move data from a PCI/X port to SDRAM
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80314 I/O Processor Companion Chip Datasheet
80314 I/O Processor Companion Chip Design Guide
80314 I/O Processor Companion Chip Design Guide
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
80314 I/O Processor Companion Chip Developer’s Manual
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80314 I/O Processor Companion Chip Developer’s Manual incorrectly states that the
80314 I/O Processor Companion Chip Developer’s Manual incorrectly defines the
Intel
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80314 I/O Processor Companion Chip Developer’s Manual incorrectly
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80314 I/O Processor Companion Chip Design Guide incorrectly states
80314 I/O Processor Companion Chip Specification Update