EW80314GN S L8AZ Intel, EW80314GN S L8AZ Datasheet - Page 21

• Manufacturer Part Number: EW80314GN S L8AZ
• Manufacturer: Intel

Specifications of EW80314GN S L8AZ

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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Intel
®
80314 I/O Processor Companion Chip Specification Update
Extra clock cycle on SRAM reads
When making multiple 32-byte reads to internal SRAM, there is a dead clock cycle inserted
between the 32-byte accesses.
Performance on multiple 32-byte reads to SRAM may be impacted by up to 20%.
None
Fixed
Use of MSI
The MM_CAP[2:0] field in the P_MSIC register at offset 0x0E0 cannot be changed from its
default value of four messages.
In an environment where another agent is configuring MSI, the 80314 does not support MSI
functionality, since the configuring agent may allocate less than four messages, which the 80314
would be unable to accommodate.
Use legacy interrupts.
Fixed
IRP_INTAD must be used to mask PCI INTs
The P_INT bit in the IRP_ENABLE register at offset 0x188 does not function as documented. The
IRP_INTAD register at offset 0x18C can be used to selectively mask INTA–D interrupt inputs for
passing to the internal interrupt controller, and IRP_ENABLE[P_INT] is designed to allow
masking all (the “OR”) of the A–D interrupts from being passed to the MPIC. Instead, the INTA–D
interrupts are passed to the MPIC, regardless of the setting of IRP_ENABLE[P_INT].
The P_INT bit in the IRP_ENABLE register cannot be used to mask interrupts.
Use the IRP_INTAD register to mask INTA–D.
Fixed
MemRead DWORD transaction writes to reserved bits
As an initiator, the 80314 drives a value of 0x8 on AD[7:0] during the attribute phase. This
behavior occurs only when doing a MemRead DWORD transaction.
The PCI-X 1.0a specification defines these bits as reserved.
None
Fixed
PFAB_CSR TEA bit is not functional
The PFAB_CSR register time-out bit located at bit 28 does not get set on a time-out.
None
None
Fixed
Errata
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