MT48LC16M16A2P-7E:D Micron Technology Inc, MT48LC16M16A2P-7E:D Datasheet - Page 27

• Manufacturer Part Number: MT48LC16M16A2P-7E:D
• Description: SDRAM 256MB, SMD, 48LC16, TSOP54
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC16M16A2P-7E:D

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Package / Case: TSOP
• Memory Type: DRAM - Synchronous
• Memory Configuration: 4 BLK (4M X 16)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Format - Memory: RAM
• Memory Size: 256M (16Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Compliant

Figure 17:
WRITEs
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_2.fm - Rev. M 10/07 EN
Terminating a READ Burst
Note:
COMMAND
WRITE bursts are initiated with a WRITE command, as shown in Figure 18 on page 28.
The starting column and bank addresses are provided with the WRITE command, and
auto precharge is either enabled or disabled for that access. If auto precharge is enabled,
the row being accessed is precharged at the completion of the burst. For the generic
WRITE commands used in the following illustrations, auto precharge is disabled.
During WRITE bursts, the first valid data-in element will be registered coincident with
the WRITE command. Subsequent data elements will be registered on each successive
positive clock edge. Upon completion of a fixed-length burst, assuming no other
commands have been initiated, the DQs will remain High-Z, and any additional input
data will be ignored (see Figure 19 on page 28). A full-page burst will continue until
terminated. (At the end of the page, it will wrap to column 0 and continue.)
Data for any WRITE burst may be truncated with a subsequent WRITE command, and
data for a fixed-length WRITE burst may be immediately followed by data for a WRITE
command. The new WRITE command can be issued on any clock following the previous
WRITE command, and the data provided coincident with the new command applies to
the new command.
COMMAND
ADDRESS
ADDRESS
DQM is LOW.
CLK
CLK
DQ
DQ
BANK a,
BANK a,
T0
COL n
COL n
T0
READ
READ
CL = 2
T1
T1
NOP
NOP
CL = 3
T2
T2
NOP
NOP
27
D
OUT
n
T3
T3
NOP
NOP
D
n + 1
D
OUT
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
TRANSITIONING DATA
PRECHARGE
PRECHARGE
(a or all)
(a or all)
BANK
BANK
T4
T4
X = 1 cycle
n + 2
D
n + 1
D
OUT
OUT
X = 2 cycles
T5
T5
NOP
NOP
n + 2
n + 3
D
D
OUT
OUT
t RP
t RP
64Mb: x4, x8, x16 SDRAM
T6
T6
NOP
NOP
n + 3
D
OUT
©2000 Micron Technology, Inc. All rights reserved.
DON’T CARE
BANK a,
BANK a,
ACTIVE
ACTIVE
T7
T7
ROW
ROW
Commands