MT48LC16M16A2P-7E:D Micron Technology Inc, MT48LC16M16A2P-7E:D Datasheet - Page 2

• Manufacturer Part Number: MT48LC16M16A2P-7E:D
• Description: SDRAM 256MB, SMD, 48LC16, TSOP54
• Manufacturer: Micron Technology Inc
• Type: SDRAMr
• Series: -r

Specifications of MT48LC16M16A2P-7E:D

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 5.4ns
• Maximum Clock Rate: 143MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 135mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Access Time: RoHS Compliant
• Memory Case Style: TSOP
• No. Of Pins: 54
• Operating Temperature Range: 0°C To +70°C
• Operating Temperature Max: 70°C
• Operating Temperature Min: 0°C
• Package / Case: TSOP
• Memory Type: DRAM - Synchronous
• Memory Configuration: 4 BLK (4M X 16)
• Interface Type: LVTTL
• Rohs Compliant: Yes
• Format - Memory: RAM
• Memory Size: 256M (16Mx16)
• Speed: 133MHz
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Lead Free Status / RoHS Status: Compliant
• Lead Free Status / RoHS Status: Compliant

Table 3:
General Description
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
64MSDRAM_1.fm - Rev. M 10/07 EN
64Mb SDRAM Part Numbers
Notes:
1. FBGA Device Decoder: http://www.micron.com/support/FBGA/FBGA.asp
The Micron
containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns
by 4 bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns
by 8 bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256
columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-
tions, or the full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
fully random access. Precharging one bank while accessing one of the other three banks
will hide the precharge cycles and provide seamless, high-speed, random-access
operation.
The 64Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode
is provided, along with a power-saving, power-down mode. All inputs and outputs are
LVTTL-compatible.
SDRAMs offer substantial advances in DRAM operating performance, including the
ability to synchronously burst data at a high data rate with automatic column-address
generation, the ability to interleave between internal banks in order to hide precharge
time, and the capability to randomly change column addresses on each clock cycle
during a burst access.
MT48LC16M4A2TG
MT48LC16M4A2P
MT48LC8M8A2TG
MT48LC8M8A2P
MT48LC4M16A2TG
MT48LC4M16A2P
MT48LC4M16A2B4
MT48LC4M16A2F4
Part Numbers
®
64Mb SDRAM is a high-speed CMOS, dynamic random-access memory
1
1
2
Architecture
16 Meg x 4
16 Meg x 4
4 Meg x 16
4 Meg x 16
4 Meg x 16
4 Meg x 16
Micron Technology, Inc., reserves the right to change products or specifications without notice.
8 Meg x 8
8 Meg x 8
64Mb: x4, x8, x16 SDRAM
General Description
©2000 Micron Technology, Inc. All rights reserved.
54-ball VFBGA
54-ball VFBGA
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
54-pin TSOP II
Package