PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 73

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

4.2
Register 4-1
the RAM and Flash memory partitions for data and
code.
REGISTER 4-1:
© 2011-2012 Microchip Technology Inc.
Legend:
R = Readable bit
-n = Value at POR
bit 31-21 Unimplemented: Read as ‘0’
bit 20
bit 19
bit 18
bit 17
bit 16
bit 15-7
bit 6
bit 5-3
bit 2-0
Range
31:24
23:16
15:8
Bit
7:0
Control Registers
BMXERRIXI: Enable Bus Error from IXI bit
1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
BMXERRICD: Enable Bus Error from ICD Debug Unit bit
1 = Enable bus error exceptions for unmapped address accesses initiated from ICD
0 = Disable bus error exceptions for unmapped address accesses initiated from ICD
BMXERRDMA: Bus Error from DMA bit
1 = Enable bus error exceptions for unmapped address accesses initiated from DMA
0 = Disable bus error exceptions for unmapped address accesses initiated from DMA
BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access
BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
Unimplemented: Read as ‘0’
BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit
1 = Data RAM accesses from CPU have one wait state for address setup
0 = Data RAM accesses from CPU have zero wait states for address setup
Unimplemented: Read as ‘0’
BMXARB<2:0>: Bus Matrix Arbitration Mode bits
111 = Reserved (using these Configuration modes will produce undefined behavior)
•
•
•
011 = Reserved (using these Configuration modes will produce undefined behavior)
010 = Arbitration Mode 2
001 = Arbitration Mode 1 (default)
000 = Arbitration Mode 0
31/23/15/7
through
Bit
U-0
U-0
U-0
U-0
—
—
—
—
Register 4-8
BMXCON: BUS MATRIX CONFIGURATION REGISTER
30/22/14/6
WSDRM
R/W-1
BMX
Bit
U-0
U-0
U-0
—
—
—
are used for setting
W = Writable bit
‘1’ = Bit is set
29/21/13/5
Bit
U-0
U-0
U-0
U-0
—
—
—
—
Preliminary
28/20/12/4
ERRIXI
R/W-1
BMX
Bit
U-0
U-0
U-0
—
—
—
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
27/19/11/3
ERRICD
R/W-1
BMX
Bit
U-0
U-0
U-0
—
—
—
PIC32MX1XX/2XX
26/18/10/2
ERRDMA
R/W-1
BMX
R/W-0
Bit
U-0
U-0
—
—
BMXARB<2:0>
25/17/9/1
ERRDS
R/W-1
BMX
R/W-0
Bit
U-0
U-0
—
—
DS61168D-page 73
24/16/8/0
ERRIS
R/W-1
BMX
R/W-1
Bit
U-0
U-0
—
—