PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 160

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 14-1:
DS61168D-page 160
Legend:
R = Readable bit
-n = Bit Value at POR: (‘0’, ‘1’, x = unknown)
bit 31-16
bit 15
bit 14
bit 13
bit 12-10
bit 9
bit 8
bit 7
bit 6-5
bit 4
bit 3
Note 1:
Bit Range
31:24
23:16
15:8
7:0
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
Unimplemented: Read as ‘0’
ON: Input Capture Module Enable bit
1 = Module enabled
0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
Unimplemented: Read as ‘0’
SIDL: Stop in Idle Control bit
1 = Halt in CPU Idle mode
0 = Continue to operate in CPU Idle mode
Unimplemented: Read as ‘0’
FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110)
1 = Capture rising edge first
0 = Capture falling edge first
C32: 32-bit Capture Select bit
1 = 32-bit timer resource capture
0 = 16-bit timer resource capture
ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is ‘1’)
0 = Timer3 is the counter source for capture
1 = Timer2 is the counter source for capture
ICI<1:0>: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow occurred
0 = No input capture overflow occurred
ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read
0 = Input capture buffer is empty
31/23/15/7
ICTMR
ON
R/W-0
R/W-0
Bit
U-0
U-0
—
—
(1)
IC
X
CON: INPUT CAPTURE
30/22/14/6
R/W-0
Bit
U-0
U-0
U-0
—
—
—
ICI<1:0>
W = Writable bit
29/21/13/5
R/W-0
SIDL
R/W-0
Bit
U-0
U-0
—
—
Preliminary
(1)
X
28/20/12/4
CONTROL REGISTER
ICOV
Bit
U-0
U-0
U-0
R-0
—
—
—
U = Unimplemented bit
P = Programmable bit
27/19/11/3
ICBNE
Bit
U-0
U-0
U-0
R-0
—
—
—
26/18/10/2
© 2011-2012 Microchip Technology Inc.
R/W-0
Bit
U-0
U-0
U-0
—
—
—
r = Reserved bit
ICM<2:0>
25/17/9/1
FEDGE
R/W-0
R/W-0
Bit
U-0
U-0
—
—
24/16/8/0
R/W-0
R/W-0
C32
Bit
U-0
U-0
—
—