PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 158

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PIC32MX210F016B-I/SO

Manufacturer Part Number
PIC32MX210F016B-I/SO
Description
PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
Manufacturer
Microchip Technology
Datasheet
PIC32MX1XX/2XX
REGISTER 13-1:
DS61168D-page 158
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
4:
When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
This bit is available only on even numbered timers (Timer2 and Timer4).
While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and
Timer5). All timer functions are set through the even numbered timers.
While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.
T32: 32-Bit Timer Mode Select bit
1 = Odd numbered and even numbered timers form a 32-bit timer
0 = Odd numbered and even numbered timers form a separate 16-bit timer
Unimplemented: Read as ‘0’
TCS: Timer Clock Source Select bit
1 = External clock from TxCK pin
0 = Internal peripheral clock
Unimplemented: Read as ‘0’
TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED)
(2)
(3)
Preliminary
© 2011-2012 Microchip Technology Inc.

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