PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 147

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

11.3.5
In contrast to inputs, the outputs of the peripheral pin
select options are mapped on the basis of the pin. In
this case, a control register associated with a
particular pin dictates the peripheral output to be
mapped. The RPnR registers
used to control output mapping. Like the [pin name]R
registers, each register contains sets of 4 bit fields.
The value of the bit field corresponds to one of the
peripherals, and that peripheral’s output is mapped
to the pin (see
A null output is associated with the output register reset
value of ‘0’. This is done to ensure that remappable
outputs remain disconnected from all output pins by
default.
FIGURE 11-3:
11.3.6
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC32 devices include two features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Configuration bit select lock
© 2011-2012 Microchip Technology Inc.
U1RTS Output
U1TX Output
OUTPUT MAPPING
CONTROLLING CONFIGURATION
CHANGES
Table 11-2
Default
RPA0R<3:0>
EXAMPLE OF
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPA0
14
15
0
1
2
and
Output Data
Figure
(Register
11-3).
11-2) are
RPA0
Preliminary
11.3.6.1
Under normal operation, writes to the RPnR and [pin
name]R registers are not allowed. Attempted writes
appear to execute normally, but the contents of the
registers remain unchanged. To change these regis-
ters, they must be unlocked in hardware. The regis-
ter lock is controlled by the IOLOCK Configuration bit
(CFGCON<13>). Setting IOLOCK prevents writes to
the control registers; clearing IOLOCK allows writes.
To set or clear the IOLOCK bit, an unlock sequence
must be executed. Refer to Section 6. “Oscillator”
(DS61112) in the “PIC32 Family Reference Manual” for
details.
11.3.6.2
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPnR and [pin name]R registers. The IOL1WAY
Configuration bit (DEVCFG3<29>) blocks the IOLOCK
bit from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure
does not execute, and the peripheral pin select control
registers cannot be written to. The only way to clear the
bit and re-enable peripheral remapping is to perform a
device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session.
PIC32MX1XX/2XX
Control Register Lock
Configuration Bit Select Lock
DS61168D-page 147