PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 236

• Manufacturer Part Number: PIC32MX210F016B-I/SO
• Description: PIC32, 16KB Flash, 4KB RAM, 40 MHz, USB, CTMU, 4 DMA 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology

PIC32MX1XX/2XX
REGISTER 26-7:
DS61168D-page 236
Legend:
R = Readable bit
-n = Value at POR
bit 31-16 Unimplemented: Read as ‘0’
bit 15
bit 14-7
bit 6-2
bit 1
bit 0
Note 1:
Range
31:24
23:16
15:8
7:0
Bit
2:
ON: Watchdog Timer Enable bit
1 = Enables the WDT if it is not enabled by the device configuration
0 = Disable the WDT if it was enabled in software
Unimplemented: Read as ‘0’
SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits
On reset, these bits are set to the values of the WDTPS <4:0> of Configuration bits.
WDTWINEN: Watchdog Timer Window Enable bit
1 = Enable windowed Watchdog Timer
0 = Disable windowed Watchdog Timer
WDTCLR: Watchdog Timer Reset bit
1 = Writing a ‘1’ will clear the WDT
0 = Software cannot force this bit to a ‘0’
A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software.
When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
31/23/15/7
ON
R/W-0
Bit
U-0
U-0
U-0
—
—
—
(1,2)
WDTCON: WATCHDOG TIMER CONTROL REGISTER
30/22/14/6
Bit
U-0
U-0
U-0
R-y
—
—
—
y = Values set from Configuration bits on POR
W = Writable bit
‘1’ = Bit is set
29/21/13/5
(1,2)
Bit
U-0
U-0
U-0
R-y
—
—
—
SWDTPS<4:0>
Preliminary
28/20/12/4
Bit
U-0
U-0
U-0
R-y
—
—
—
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
27/19/11/3
Bit
U-0
U-0
U-0
R-y
—
—
—
26/18/10/2
© 2011-2012 Microchip Technology Inc.
Bit
U-0
U-0
U-0
R-y
—
—
—
(1,2,3)
WDTWINEN WDTCLR
x = Bit is unknown
25/17/9/1
R/W-0
Bit
U-0
U-0
U-0
—
—
—
24/16/8/0
R/W-0
Bit
U-0
U-0
U-0
—
—
—