PIC32MX210F016B-I/SO Microchip Technology, PIC32MX210F016B-I/SO Datasheet - Page 53

All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See

information.

x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

more information.

31:16

15:0

31:16

15:0

DMA GLOBAL REGISTER MAP

DMA CRC REGISTER MAP

31/15

—

30/14

—

29/13

—

BYTO<1:0>

SUSPEND DMABUSY

28/12

(1)

—

(1)

27/11

WBO

—

PLEN<4:0>

26/10

—

25/9

—

DMAADDR<31:0>

DCRCDATA<31:0>

DCRCXOR<31:0>

24/8

BITO

24/8

—

Bits

CRCEN

23/7

—

CRCAPP CRCTYP

22/6

—

21/5

—

20/4

—

Section 11.2 “CLR, SET and INV Registers”

RDWR

Section 11.2 “CLR, SET and INV Registers”

19/3

—

18/2

—

DMACH<2:0>

CRCCH<2:0>

17/1

—

(2)

16/0

—

for more

0000

for

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PIC32MX210F016B-I/SO

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