CY7C924ADX-AC Cypress Semiconductor Corp, CY7C924ADX-AC Datasheet - Page 46

• Manufacturer Part Number: CY7C924ADX-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AC

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
the Transmit FIFO can still accept up to eight additional writes
of data. When a Full state is asserted due to a Transmit FIFO
reset operation, the FIFO will not accept any additional data.
This FIFO reset operation is not allowed to progress within the
device until the external reset condition is removed. This can
occur by deasserting TXRST* or AM*. If AM* is deasserted
(HIGH) to remove the reset condition, the Transmit FIFO flag’s
drivers are disabled, and the Transmit FIFO must be
addressed at a later time to validate completion of the Transmit
FIFO reset. If TXRST* is deasserted (HIGH) to remove the
reset condition, the Tx_RstMatch is changed to a Tx_Match,
and the Transmit FIFO status flags remain driven.
The Transmit FIFO reset operation is complete when the
Transmit FIFO flags indicate an Empty state (TXEMPTY* is
asserted and both TXHALF* and TXFULL* are deasserted). A
valid Transmit FIFO reset sequence is shown in
Figure 14 on page 47
does not produce a FIFO reset. In this case TXEN* was
asserted to select the a Transmit FIFO for data transfers.
Because TXEN* remains active, the assertion of AM* and
TXRST* does not initiate a reset operation. This is shown by
the TXFULL* flag remaining HIGH (deasserted) following what
would be the normal expiration of the eight-state reset counter.
Tx_FIFO_Reset
Tx_RstMatch
TXEMPTY*
Tx_Match
TXFULL*
TXRST*
TXCLK
TXEN*
AM*
shows a sequence of input signals which
[26]
[26]
[26]
Note 27
Note 27
Note 27
Figure 13. Transmit FIFO Reset Sequence
Figure
Not Empty
Not Full
13.
Receive FIFO Reset Sequence
The Receive FIFO reset sequence operates similarly to the
Transmit FIFO reset sequence. The same requirements exist
for the assertion state of RXRST* and selection of the interface
through AM*. A sample Receive FIFO reset sequence is
shown in
FIFO reset, the Receive FIFO flags are forced to indicate an
Empty state to prohibit additional reads from the FIFO. Unlike
the Transmit FIFO, where the internal completion of the reset
operation is shown by first going Full and later going Empty
when the internal reset is complete, there is no secondary
indication of the completion of the internal reset of the Receive
FIFO. The Receive FIFO is usable as soon as new data is
placed into it by the Receive Control State Machine.
When a Receive FIFO reset sequence is enabled and has
been active for at least eight RXCLK cycles, a Receive FIFO
reset operation is started. This FIFO reset operation is not
allowed to progress within the device until the associated
RXRST* or AM* signal is sampled deasserted. Following
deassertion of RXRST* (which starts the FIFO reset
operation), selection of the device for normal data transfers is
inhibited during the immediately following RXCLK clock cycle.
If a selection of the receive interface is attempted during this
immediately following cycle (by asserting RXEN*), the
selection is ignored, and the device remains unselected until
RXEN* is deasserted, and reasserted in a following RXCLK
cycle.
Figure 15 on page
47. Upon recognition of a Receive
Full
CY7C924ADX
Not Full
Empty
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