CY7C924ADX-AC Cypress Semiconductor Corp, CY7C924ADX-AC Datasheet - Page 45

• Manufacturer Part Number: CY7C924ADX-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AC

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
If RXEN* is deasserted when AM* is deasserted, AM* must
again be sampled LOW followed by RXEN* sampled low at
least one cycle later for the Receive interface to again be
selected. When the Receive interface is not selected, the
RXDATA[11:0] bus is High-Z.
The Receive FIFO flags depend only on the state of AM*.
When AM* is asserted, the flags are enabled. When AM* is
deasserted, the flags are High-Z.)
Continuous Selection
Continuous Selection is a specialized form of selection which
does not require sequenced assertion of AM* and TXEN* or
RXEN* to select the device for data transfers. In this
Continuous Selection mode, the AM* and associated TXEN*
or RXEN* enable signal must be asserted when the device is
powered up or during assertion of RESET*[1:0]. So long as
these signals remain asserted, the device remains selected
and data is accepted and presented on every clock cycle.
Note. The use of continuous selection makes it impossible to
reset the internal FIFOs, or to access the Serial Address
Register.
FIFO Reset Address Match
When AM* and TXRST* are both LOW, and this condition is
sampled by the rising edge of TXCLK, a Tx_RstMatch
condition is generated. This Tx_RstMatch condition continues
until AM* or TXRST* is sampled HIGH by the rising edge of
TXCLK. When a Tx_RstMatch (or Tx_Match) condition is
present, the TXEMPTY* and TXFULL* output drivers are
enabled (just as in a normal Tx_Match condition). When AM*
is not asserted, these same drivers are disabled (High-Z). The
Transmit FIFO reset Address Match is shown in
Note that although TXRST* remains LOW for more than one
clock cycle, the Tx_RstMatch does not because the AM*
signal is no longer asserted (LOW).
When AM* and RXRST* are both LOW, and this condition is
sampled by the rising edge of RXCLK, an Rx_RstMatch
condition is generated. This Rx_RstMatch condition continues
until AM* or RXRST* is sampled HIGH, at the rising edge of
RXCLK. When an Rx_RstMatch (or Rx_Match) condition is
present, the RXEMPTY* and RXFULL* output drivers are
enabled. When AM* is not asserted these same drivers are
Tx_RstMatch
Figure 11. Transmit FIFO Reset Address Match
Tx_Match
TXFULL*
TXRST*
TXCLK
AM*
[26]
[26]
Valid
Figure
11.
disabled (High-Z). The Receive FIFO reset Address Match is
shown in
Note that while the FIFO flags remain asserted for more than
one clock cycle, this is due to an Rx_Match condition, not a
continuation of the Rx_RstMatch.
FIFO Reset Sequence
On power-up, the Transmitter and Receiver FIFOs are cleared
automatically. If the usage of the FIFOs in specific operating
modes results in stale or unwanted data, this data can be
cleared by resetting the respective FIFO. Data in the Transmit
FIFO will empty automatically if it is enabled to read the FIFO
(assuming TXHALT* is not LOW). Stale received data can be
“flushed” by reading it, or the Receive FIFO can be reset to
remove the unwanted data.
The Transmit and Receive FIFOs are reset when the
Tx_RstMatch or Rx_RstMatch condition remains present for
eight consecutive clock cycles. Any disruption of the reset
sequence prior to reaching the eight cycle count, either by
removal of AM* or the respective TXRST* or RXRST* termi-
nates the sequence and does not reset the FIFO. If the
associated TXEN* or RXEN* signals are asserted during the
reset, the relevant interface’s reset operation is inhibited until
the enable signal is deasserted. Because AM* must remain
asserted during the reset sequence, the addressed FIFO flags
remain driven during the entire sequence.
Transmit FIFO Reset Sequence
The Transmit FIFO reset sequence is started when TXRST*
and AM* are first sampled LOW by the rising edge of TXCLK.
If TXEN* is asserted (sampled HIGH for UTOPIA timing or
LOW for Cascade timing), the reset sequence is inhibited until
it is removed.
When a Transmit FIFO reset sequence is enabled and has
been active for at least eight TXCLK cycles, a Transmit FIFO
reset operation is started. To show this progress, the Transmit
FIFO flags are forced to indicate a FULL* condition
(TXEMPTY* is deasserted, and both TXHALF* and TXFULL*
are asserted).
Note. The FIFO Full state forced by the reset operation is
different from a Full state caused by normal FIFO data writes.
For normal FIFO write operations, when Full is first asserted,
Rx_RstMatch
RXEMPTY
Rx_Match
Figure 12. Receive FIFO Reset Address Match
RXRST*
RXCLK
Figure
AM*
[26]
[26]
12.
Valid
CY7C924ADX
Valid
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