CY7C924ADX-AC Cypress Semiconductor Corp, CY7C924ADX-AC Datasheet - Page 28

• Manufacturer Part Number: CY7C924ADX-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AC

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
CY7C924ADX Receiver TTL Switching Characteristics, FIFO Enabled
CY7C924ADX Transmitter TTL Switching Characteristics, FIFO Bypassed
Note
11. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads.
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
RIS
RXCLKIP
RXCPWH
RXCPWL
RXCLKIR
RXCLKIF
RXENS
RXENH
RXRSS
RXRSH
RXAMS
RXAMH
RXA
RXZA
RXOE
RXAZ
TRA
REFDS
REFDH
REFENS
REFENH
REFAMS
REFAMH
REFZA
REFOE
REFAZ
Parameter
Parameter
[11]
[11]
[11]
[11]
[8]
[8]
RXCLK Clock Cycle Frequency With Receive FIFO Enabled
RXCLK Input Period
RXCLK Input HIGH Time
RXCLK Input LOW Time
RXCLK Input Rise Time
RXCLK Input Fall Time
Receive Enable Setup Time to RXCLK↑
Receive Enable Hold Time from RXCLK↑
Receive FIFO Reset (RXRXT*) Setup Time to RXCLK↑
Receive FIFO Reset (RXRXT*) Hold Time from RXCLK↑
Receive Address Match (AM*) Setup Time to RXCLK↑
Receive Address Match (AM*) Hold Time from RXCLK↑
Flag and Data Access Time from RXCLK↑ to Output
Sample of AM* LOW by RXCLK↑, Output High-Z to Active HIGH or LOW,
or Sample of RXEN* Asserted by RXCLK↑, Output High-Z to Active HIGH or LOW
Sample of AM* LOW by RXCLK↑ to Output Valid,
or Sample of RXEN* Asserted by RXCLK↑ to RXDATA Outputs Valid
Sample of AM* HIGH by RXCLK↑ to Output in High-Z,
or Sample of RXEN* Deasserted by RXCLK↑ to RXDATA Outputs in High-Z
Flag Access Time From REFCLK↑ to Output
Write Data Set-Up Time to REFCLK↑
Write Data Hold Time from REFCLK↑
Transmit Enable Setup Time to REFCLK↑
Transmit Enable Hold Time from REFCLK↑
Transmit Address Match (AM*) Setup Time to REFCLK↑
Transmit Address Match (AM*) Hold Time from REFCLK↑
Sample of AM* LOW by REFCLK↑, Output High-Z to Active HIGH or LOW
Sample of AM* LOW by REFCLK↑ to Flag Output Valid
Sample of AM* HIGH by REFCLK↑ to Flag Output High-Z
[10]
[10]
Description
Description
[11]
[11]
Over the Operating Range
Over the Operating Range
CY7C924ADX
Min
Min
6.5
6.5
0.7
0.7
1.5
1.5
1.5
1.5
1.5
20
2
4
2
4
2
4
2
0
4
1
4
1
4
1
0
Page 28 of 58
Max
Max
50
20
20
15
20
20
15
5
5
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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