CY7C924ADX-AC Cypress Semiconductor Corp, CY7C924ADX-AC Datasheet - Page 40

• Manufacturer Part Number: CY7C924ADX-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AC

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
The TXEMPTY* flag, when used for transmit BIST progress
indication, continues to reflect the active HIGH or active LOW
settings determined by the UTOPIA or Cascade timing model
selected by EXTFIFO; i.e., when configured for the Cascade
timing model, the TXEMPTY* and TXFULL* FIFO flags are
active HIGH, when configured for the UTOPIA timing model
the TXEMPTY* and TXFULL* FIFO flags are active LOW. The
illustration in Figure 7 uses the UTOPIA conventions.
When TXBISTEN* is first recognized, the TXEMPTY* flag is
clocked to a reset state, regardless of the addressed state of
the Transmit FIFO (if AM* is LOW or not), but is not driven out
of the part unless AM* has been sampled asserted (LOW).
Following this, on each completed pass through the BIST loop,
the TXEMPTY* flag is set for one interface clock period
(TXCLK or REFCLK).
When the Transmit FIFO is enabled, the TXEMPTY* flag
remains set until the interface is addressed and the state of
TXEMPTY* has been observed. If the device is not addressed
(AM* is not sampled LOW), the flag remains set internally
regardless of the number of TXCLK clock cycles that are
processed. If the device status is not polled on a sufficiently
regular basis, it is possible for the host system to miss one or
more of these BIST loop indications.
A pass through the loop is defined as that condition where the
Encoder generates the D0.0 state that initiates the BIST loop.
Enable TX BIST
Enable RX BIST
Start of TX BIST
Start of RX
BIST Wait
BIST match
Start of RX
Figure 7. Built-In Self-Test Illustration, UTOPIA Mode
Forced to indicate EMPTY by BIST
ERROR
LOOP
BIST
LOW to enable RXRVS reads
LOW to enable FIFO Flags
Ignore these outputs
LOOP
BIST
Don’t Care
Depending on the initial state of the BIST LFSR, the first pass
through the loop may occur at substantially less than 511
character periods. Following the first pass, as long as
TXBISTEN* remains LOW, all remaining passes are exactly
511 characters in length.
When the Transmit FIFO is bypassed, the interface is clocked
by the REFCLK signal instead of TXCLK. While the active or
asserted state of the TXEMPTY* signal is still controlled by the
EXTFIFO, the state of any completed BIST loops is no longer
preserved. Instead, the TXEMPTY* flag reflects the dynamic
state of the BIST loop progress, and is asserted only once
every 511 character periods. If the interface is not addressed
at the time that this occurs, then the FIFO status flags remain
in a High-Z state and the loop event is lost.
BIST Receive Path
The receive path operation in BIST is similar to that of the
transmit path. While the Receive FIFO is enabled and
RXBISTEN* is recognized internally, all writes to the Receive
FIFO are suspended. If the receiver had a previous serial
address match and was accepting data, no additional
characters are written to the Receive FIFO. If the receive data
state machine was in the middle of processing a
multi-character sequence or other atomic operation (e.g., a
start of cell marker and its associated data), the characters
TXCLK
TXBISTEN*
TXEMPTY*
TXHALF*
TXFULL*
TXSVS
TXSOC
TXSC/D*
TXDATA[9:0]
TXEN*
REFCLK
AM*
RXEN*
RXDATA[9:0]
RXSC/D*
RXSOC
RXRVS
RXEMPTY*
RXHALF*
RXFULL*
RXBISTEN*
RXCLK
OUTA±
OUTB±
INA±
INB±
A/B*
CY7C924ADX
HIGH to select A
Page 40 of 58
[+] Feedback