CY7C924ADX-AC Cypress Semiconductor Corp, CY7C924ADX-AC Datasheet - Page 16

• Manufacturer Part Number: CY7C924ADX-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AC

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
encoder on the first clock cycle. During the second clock cycle
the remaining two bits of the first character are combined with
the lower six bits of the second 10 bit character (B[5:0]+A[9:8]).
In the third clock cycle the remaining four bits of the second 10
bit character are combined with the lower four bits of the third
10 bit character (C[3:0]+B[9:6]). In the fourth clock cycle the
remaining six bits of the third 10 bit character are combined
with the lower two bits of the fourth 10 bit character
(D[1:0]+C[9:4]). In the fifth clock cycle the remaining eight bits
of the fourth 10 bit character are passed to the encoder
(D[9:2]).
This process repeats for additional data characters present in
the FIFO. If at any time the Transmit FIFO is emptied, and a
portion of a 10 bit character has not yet been transmitted, the
remaining bits of the 8 bit character are filled with dummy bits
before that character is passed to the encoder. The 8 bit
character containing these dummy bits is immediately
followed by a C5.0 (K28.5) fill character, which resets the
sequencer boundaries to the first character position.
Encoder Block
The Encoder logic block performs two primary functions:
encoding the data for serial transmission and generating BIST
(Built-In Self-Test) patterns to allow at speed link and device
testing.
BIST LFSR
The Encoder logic block operates on data stored in a register.
This register accepts information directly from the Transmit
FIFO, the Transmit Input Register, the 10/8 Byte Packer, or
from the Transmit Control State Machine when it inserts
special characters into the data stream.
This same register is converted into a Linear Feedback Shift
Register (LFSR) when the Built-In Self-Test (BIST) pattern
generator is enabled (TXBISTEN* is LOW). When enabled,
this LFSR generates a 511-character sequence that includes
DDDDDDDD
98765432
Character
DDDDDDDDDD
9876543210
Figure 4. Byte-Packer 10-to-8 Character Mapping
Sent
Last
DDCCCCCC
10987654
Source 10-bit Character Stream
CCCCCCCCCC
9876543210
CCCCBBBB
32109876
BBBBBBBBBB
9876543210
BBBBBBAA
54321098
AAAAAAAAAA
9876543210
Character
AAAAAAAA
76543210
Sent
First
all Data and Special Character codes, including the explicit
violation
pseudo-random sequence that can be matched to an identical
LFSR in the Receiver.
The specific patterns generated are described in detail in the
Cypress application note “HOTLink Built-In Self-Test.” The
sequence generated by the CY7C924ADX is identical to that
in
CYP(V)15G0x0x, allowing the user to build interoperable
systems when the devices are used at compatible serial
signaling rates.
Encoder
The data passed through the Transmit FIFO and formatter, or
as received directly from the Transmit Input Register, is
seldom in a form suitable for transmission across a serial link.
The characters must usually be processed or transformed to
guarantee:
The CY7C924ADX contains an integrated 8B/10B encoder
that accepts 8 bit data characters and converts these into 10
bit transmission characters that have been optimized for
transport on serial communications links. The 8B/10B encoder
can be bypassed for those system that operate with external
8B/10B encoders, or use alternate forms of encoding or
scrambling to ensure good transmission characteristics. The
operation of the 8B/10B encoding algorithm is described in
detail later in this data sheet, and the complete encoding
tables are listed in
55.
When the Encoder is enabled, the transmit data characters (as
passed through the Transmit FIFO and formatter) are
converted to either a 10 bit Data symbol or a 10 bit Special
Character, depending upon the state of the TXSC/D* input. If
TXSC/D* is HIGH, the data inputs represent a Special
Character code and are encoded using the Special Character
encoding rules in
are encoded using the Data Character encoding in
If TXSVS is HIGH, the respective character is replaced with an
SVS (C0.7) character. This can be used to check error
handling system logic in the receiver controller or for propri-
etary applications.
The 8B/10B encoder is compliant with ANSI/NCITS ASC
X3.230-1994 (Fibre Channel), IEEE 802.3z (Gigabit Ethernet),
the IBM ESCON and FICON channels, and ATM Forum
standards for data transport.
The 8B/10B coding function of the Encoder can be bypassed
for systems that include an external coder or scrambler
function as part of the controller or host system. Do this by
setting ENCBYP* LOW. With the encoder bypassed, each
10 bit or 12 bit character (as captured in the Transmit Input
Register) passes directly to the Transmit Shifter (or Transmit
FIFO) without modification.
• A minimum transition density (to allow the serial receiver
• A DC balance in the signaling (to prevent baseline wander)
• Run length limits in the serial data (to limit the bandwidth of
• A way to allow the remote receiver to determine the correct
PLL to extract a clock from the data stream)
the link)
character boundaries (framing).
the
HOTLink
symbols.
Table
Table 11 on page 51
CY7B923
This
12. If TXSC/D* is LOW, the data inputs
provides
and
CY7C924ADX
and
HOTLink
a
Table 12 on page
predictable
Page 16 of 58
Table
II
family
11.
but
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