CY7C924ADX-AC Cypress Semiconductor Corp, CY7C924ADX-AC Datasheet - Page 14

• Manufacturer Part Number: CY7C924ADX-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AC

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
CY7C924ADX HOTLink Transceiver Block
Diagram Description
Transmit Input/Output Register
The Transmit Input Register, shown in
data to be processed by the HOTLink Transmitter, and allows
the input timing to be compatible with asynchronous or
synchronous host system buses. These buses can take the
form of UTOPIA compliant interfaces, external FIFOs, state
machines, or other control structures. Data present on the
TXDATA[11:0] and TXSC/D* inputs are captured at the rising
edge of the selected sample clock. The transmit data bus bit
assignments vary depending on the data encoding, and bus
width selected. These bus bit assignments are shown in
Table 1 on page
different signals. Note that the function of several of these
signals changes in different operating modes. The logical
sense of the enable and FIFO flag signals depends on the
intended interface convention and is set by the EXTFIFO pin.
The transmit interface supports both synchronous and
asynchronous clocking modes, each supporting both UTOPIA
(EXTFIFO = LOW) and Cascade (EXTFIFO = HIGH) timing
models. The selection of the specific clocking mode is deter-
mined by the RANGESEL and SPDSEL inputs and the FIFO
Bypass (FIFOBYP*) signal.
Synchronous Interface
Synchronous interface clocking operates the entire transmit
data path synchronous to REFCLK. To enable it, connect
FIFOBYP* LOW to disable the internal FIFOs.
Asynchronous Interface
Asynchronous interface clocking controls the writing of host
bus data into the Transmit FIFO. To enable it, set FIFOBYP*
HIGH to enable the internal FIFOs. In these configurations,
TXCLK controls all writes to the Transmit Input Register and
associated transfers to the Transmit FIFO. The data is clocked
out of the Transmit FIFO and through the rest of the device on
REFCLK or a synthesized derivative of REFCLK.
To Encoder
TXDATA[11:0]
Block
Transmit Input Register
12
Figure 2. Transmit Input Register
TXSC/D*
13, and list the functional names of these
Transmit FIFO
14
TXEN*
AM*
Figure
TXCLK
2, captures the
REFCLK
UTOPIA Timing Model
The UTOPIA timing model allows multiple CY7C924ADX
transmitters to be addressed and accessed from a common
host bus, using the protocols defined in the ATM Forum
UTOPIA interface standards. To enable it, set EXTFIFO LOW.
In UTOPIA timing, the TXEMPTY* and TXFULL* outputs and
TXEN* input, are all active LOW signals. If the CY7C924ADX
is addressed by AM*, it is “selected” when TXEN* is asserted
LOW. Following selection, data is written into the Transmit
FIFO on every clock TXCLK cycle where TXEN* remains
LOW.
Cascade Timing Model
The Cascade timing model is a variation of the UTOPIA timing
model. Here the TXEMPTY* and TXFULL* outputs, and TXEN
input, are all active HIGH signals. Cascade timing uses the
same address and selection sequences as UTOPIA timing,
but write data accesses use a delayed write. This delayed
write is necessary to allow direct coupling to external FIFOs,
or to state machines that initiate a write operation one clock
cycle before the data is available on the bus. To enable
Cascade timing, set EXTFIFO HIGH.
When used for FIFO depth expansion, Cascade timing allows
the size of the internal Transmit FIFO to be expanded to an
almost unlimited depth. It makes it possible to attach a
CY7C42x5 series synchronous FIFO to the transmit interface
without any extra logic, as shown in
Transmit FIFO
The Transmit FIFO buffers data captured in the input register
for later processing and transmission. This FIFO holds 256
14-bit characters. When the Transmit FIFO is active, and a
Transmit FIFO write is enabled (the device is selected through
AM* and TXEN* is sampled asserted), data and command are
captured in the transmit input register and stored in the
Transmit FIFO. TXCLK clocks all Transmit FIFO write opera-
tions.
The Transmit FIFO presents Full, Half-Full, and Empty FIFO
flags. These flags are provided synchronous to TXCLK. When
the Transmit FIFO is enabled, it allows operation with a
Moore-type external controlling state machine. When
configured for Cascade timing, the timing and active levels of
these signals also support direct expansion to Cypress
CY7C42x5 synchronous FIFOs.
FF*
WEN*
D
TXCLK
Figure 3. External FIFO Depth Expansion of the
CY7C924ADX Transmit Data Path
CY7C42x5 FIFO
WCLK
FF*
WEN*
D
RCLK
REN*
EF*
Q
Figure
CY7C924ADX
“1”
3.
CY7C924ADX
EXTFIFO
TXEN
TXFULL
TXCLK
TXDATA
TXSC/D*
Page 14 of 58
[+] Feedback