CY7C924ADX-AC Cypress Semiconductor Corp, CY7C924ADX-AC Datasheet - Page 13

• Manufacturer Part Number: CY7C924ADX-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AC

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
Encoder
Data from the host interface or Transmit FIFO is next passed
to an encoder block. The CY7C924ADX contains an internal
8B/10B encoder that is used to improve the serial transport
characteristics of the data. For systems that contain their own
encoder or scrambler, this encoder may be bypassed.
Serializer/Line Driver
The data from the encoder is passed to a serializer. This
serializer operates at either 2.5, 5, or 10 times the rate of the
REFCLK input (or 3, 6, or 12 times when BYTE8/10* and
ENCBYP* are LOW). The serialized data is output from two
PECL-compatible differential line drivers configured to drive
transmission lines or optical modules.
Receive Data Path
Line Receiver/Deserializer/Framer
Serial data is received at one of two PECL-compatible differ-
ential line receivers. The data is passed to both a Clock and
Data Recovery PLL (Phase Locked Loop) and to a deserializer
that converts serial data into parallel characters. The framer
Table 1. Transmit Input Bus Signal Map
Notes
1. All open cells are ignored.
2. First bit shifted out. Others follow in numerical order creating an NRZ pattern.
TXDATA Bus Input Bit
TXHALT*/TXDATA[9]
TXHALT*/TXDATA[9]
TXSOC/TXDATA[11]
TXSOC/TXDATA[11]
(FIFOBYP* = HIGH)
(FIFOBYP* = HIGH)
TXSVS/TXDATA[10]
(FIFOBYP* = HIGH)
(FIFOBYP* = LOW)
(FIFOBYP* = LOW)
(FIFOBYP* = LOW)
TXINT/TXDATA[8]
TXINT/TXDATA[8]
BYTE8/10*
TXDATA[0]
TXDATA[1]
TXDATA[2]
TXDATA[3]
TXDATA[4]
TXDATA[5]
TXDATA[6]
TXDATA[7]
ENCBYP*
TXSC/D*
Character Stream
Encoded 8-bit
TXHALT*
TXSC/D*
TXSOC
TXSVS
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
TXINT
HIGH
HIGH
Pre-encoded 10-bit
Character Stream
adjusts the boundaries of these characters to match those of
the original transmitted characters.
Decoder
The parallel characters pass through a 10B/8B Decoder and
return to their original form. For systems that use external
decoding or descrambling, the decoder may be bypassed.
Receive Data Interface/Receive Data FIFO
Data from the decoder passes either to a Receive FIFO or
directly to the output register. The output register can be
configured for operation with 8 bit, 10 bit or 12 bit data
When configured for an asynchronous buffered (FIFOed)
interface, the data passes through a 256-character Receive
FIFO that allows data to be read at any rate from DC to
50 MHz. When configured for synchronous operation
(Receive FIFO is bypassed) data is clocked out of the Receive
Output register at the byte rate, up to 20 MHz. The receive
interface is also configurable for both UTOPIA and Cascade
timing models.
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
TXD[8]
TXD[8]
TXD[9]
TXD[9]
HIGH
Transmit Encoder Mode
LOW
[2]
Character Stream
Encoded 10-bit
TXSC/D*
TXSOC
TXSVS
TXD[0]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
TXD[8]
TXD[8]
TXD[9]
TXD[9]
HIGH
LOW
[1]
CY7C924ADX
Pre-encoded 12-bit
Character Stream
TXD[0]
TXD[10]
TXD[11]
TXD[11]
TXD[1]
TXD[2]
TXD[3]
TXD[4]
TXD[5]
TXD[6]
TXD[7]
TXD[8]
TXD[8]
TXD[9]
TXD[9]
Page 13 of 58
LOW
LOW
[2]
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