CY7C924ADX-AC Cypress Semiconductor Corp, CY7C924ADX-AC Datasheet - Page 29

• Manufacturer Part Number: CY7C924ADX-AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C924ADX-AC

• Number Of Transceivers: 1
• Data Rate: 622Mbps
• Operating Supply Voltage (typ): 5V
• Supply Current (max): 250mA
• Screening Level: Commercial
• Pin Count: 100
• Mounting: Surface Mount
• Package Type: TQFP
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02008 Rev. *E
CY7C924ADX Receiver TTL Switching Characteristics, FIFO Bypassed
CY7C924ADX Receiver Switching Characteristics
CY7C924ADX Transmitter Switching Characteristics
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Notes
ROS
RXCLKOP
RXCLKOD
RXCLKOR
RXCLKOF
RXENS
RXENH
RXZA
RXOE
RXAZ
B
IN_J
SA
EFW
B
RISE
FALL
DJ
RJ
JT
12. The period of f
13. Receiver UI (Unit Interval) is calculated as 1/(Serial Baud Rate), where Baud Rate is the rate of change of signaling.
14. The specification is sum of 25% Duty Cycle Distortion (DCD), 10% Data Dependant Jitter (DDJ), 15% Random Jitter (RJ).
15. The PECL switching threshold is the midpoint between the V
16. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by the absolute difference of
17. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
18. While sending continuous K28.5s, outputs loaded to 50Ω to V
19. While sending continuous K28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to REFCLK input, over the
Parameter
[15]
[15]
Parameter
Parameter
REFCLK ±2500 ppm.
the left and right edge shifts (|t
over the operating range, input jitter < 50% Dj.
operating range.
[12]
[11]
[11]
[11]
[8]
[8]
ROS
RXCLK Clock Output Frequency—100 to 200 MBaud
(RANGESEL is HIGH, ENCBYP* is HIGH or BYTE8/10* is HIGH)
RXCLK Clock Output Frequency—50 to 100 MBaud
(RANGESEL is LOW, ENCBYP* is HIGH or BYTE8/10* is HIGH)
RXCLK Clock Output Frequency—100 to 200 MBaud
12-bit Encoder Bypass Operation
(RANGESEL is HIGH, ENCBYP* is LOW and BYTE8/10* is LOW)
RXCLK Clock Output Frequency—50 to 100 MBaud 10-bit Operation
(RANGESEL is LOW, ENCBYP* is LOW and BYTE8/10* is LOW)
RXCLK Output Period
RXCLK Output Duty Cycle
RXCLK Output Rise Time
RXCLK Output Fall Time
Receive Enable Setup Time to RXCLK↑
Receive Enable Hold Time from RXCLK↑
Sample of AM* LOW by RXCLK↑, Outputs High-Z to Active
Sample of RXEN* Asserted by RXCLK↑ to RXDATA Outputs High-Z to Active
Sample of AM* LOW by RXCLK↑ to Flag Output Valid
Sample of RXEN* Asserted by RXCLK↑ to RXDATA Output Low-Z
Sample of AM* HIGH by RXCLK↑ to Flag Output High-Z
Sample of RXEN* Deasserted by RXCLK↑ to RXDATA Output High-Z
Bit Time
IN± Peak-to-Peak Input Jitter Tolerance
Static Alignment
Error Free Window
Bit Time
PECL-compatible Output Rise Time 20−80% (PECL Test Load)
PECL-compatible Output Fall Time 80−20% (PECL Test Load)
Deterministic Jitter (peak-peak)
Random Jitter (σ)
Transmitter Total Output Jitter (pk-pk)
will match the period of the transmitter PLL reference (REFCLK) when receiving serial data. When data is interrupted, RXCLK may drift to
SH_L
- t
SH_R
[8, 16]
[8, 19]
|) of one bit until a character error occurs.
[8, 13, 17]
[10]
[10]
[8, 18]
OHE
DD
Description
Description
Description
− 1.33V, over the operating range.
, and V
[8]
[13, 14]
OLE
specifications (approximately V
Over the Operating Range
Over the Operating Range
[8]
[8]
DD
Over the Operating Range
− 1.33V).
CY7C924ADX
0.65
8.33
4.16
0.25
0.25
Min
Min
Min
200
200
5.0
5.0
1.5
1.5
10
25
40
5
4
1
0
Page 29 of 58
0.008
16.67
1700
1700
Max
20.0
Max
20.0
0.02
0.08
Max
8.33
250
600
0.5
20
10
60
20
20
2
2
Unit
MHz
MHz
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
UI
ps
UI
ns
ps
ps
UI
UI
UI
%
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