82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 9

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

Table-1 Pin Description (Continued)
IDT82V2044
Pin Description
MC3/A3
MC2/A2
MC1/A1
MC0/A0
Name
CLKE
TRST
TMS
TCK
OE
A4
Pull-up
Pull-up
Type
I
I
I
I
I
I
TQFP144
114
115
12
13
14
15
16
95
96
97
Pin No.
PBGA160
G12
E14
E13
F11
F14
G3
F4
F3
F2
F1
MCn: Performance Monitor Configuration 3~0
In hardware control mode, A4 must be connected to GND. MC[3:0] are used to select one transmitter or
receiver of channel 1 to 4 for non-intrusive monitoring. Channel 0 is used as the monitoring channel. If a
transmitter is monitored, signals on the corresponding pins TTIPn and TRINGn are internally transmitted
to RTIP0 and RRING0. If a receiver is monitored, signals on the corresponding pins RTIPn and RRINGn
are internally transmitted to RTIP0 and RRING0. The clock and data recovery circuit in Receiver 0 can
then output the monitored clock to pin RCLK0 as well as the monitored data to RDP0 and RDN0 pins. The
signals monitored by channel 0 can be routed to TTIP0/TRING0 by activating Remote Loopback in this
channel.
Performance Monitor Configuration determined by MC[3:0] is shown below. Note that if MC[2:0] = 000, the
device is in normal operation of all the channels.
An: Address Bus 4~0
When pin MODE1 is low, the parallel host interface operates with separate address and data bus. In this
mode, the signal on this pin is the address bus of the host interface.
OE: Output Driver Enable
Pulling this pin low can drive all driver output into high-Z for redundancy application without external
mechanical relays. In this condition, all other internal circuits remain active.
CLKE: Clock Edge Select
The signal on this pin determines the active edge of RCLKn and SCLK in clock recovery mode, or deter-
mines the active level of RDPn and RDNn in the data recovery mode.
details.
TRST: JTAG Test Port Reset (Active Low)
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor
and can be left disconnected.
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is clocked into the device on the rising
edges of TCK. This pin has an internal pull-up resistor and it can be left disconnected.
TCK: JTAG Test Clock
This pin input the clock of the JTAG Test. The data on TDI and TMS are clocked into the device on the ris-
ing edges of TCK, while the data on TDO is clocked out of the device on the falling edges of TCK. This pin
should be connected to GNDIO or VDDIO pin when unused.
MC[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
JTAG Signals
9
Normal operation without monitoring
Normal operation without monitoring
Monitoring Configuration
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
Monitor Transmitter 1
Monitor Transmitter 2
Monitor Transmitter 3
Monitor Receiver 1
Monitor Receiver 2
Monitor Receiver 3
Reserved
Reserved
Description
See 2.3 Clock Edges on page 14
September 22, 2005
for