82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 12

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

2
2.1
unit, which contains four transmit and receive channels for use in either
T1 or E1 applications. The receiver performs clock and data recovery.
As an option, the raw sliced data (no retiming) can be output to the
system. Transmit equalization is implemented with low-impedance
output drivers that provide shaped waveforms to the transformer, guar-
anteeing template conformance. A selectable jitter attenuator may be
placed in the receive path or the transmit path. Moreover, multiple
testing functions, such as error detection, loopback and JTAG boundary
scan are also provided. The device is optimized for flexible software
control through a serial or parallel host mode interface. Hardware control
is also available.
channels operation.
2.2
Mode, the template selection pins TS[2:0], determine whether the opera-
tion mode is T1 or E1 (see
register TS determines whether the operation mode is T1 or E1.
2.2.1
in different modes:
which operation mode the device is in.
IDT82V2044
Functional Description
The IDT82V2044 is a fully integrated quad short-haul line interface
T1/E1 mode selection configures the device globally. In Hardware
The system interface of each channel can be configured to operate
Each signal pin on system side has multiple functions depending on
1. Single rail interface with clock recovery.
2. Dual rail interface with clock recovery.
3. Dual rail interface with data recovery (that is, with raw data
FUNCTIONAL DESCRIPTION
OVERVIEW
T1/E1 MODE SELECTION
SYSTEM INTERFACE
slicing only and without clock recovery).
RRINGn
TRINGn
RTIPn
Figure-1 on page 1
TTIPn
Table-9 on page
Note: The grey blocks are bypassed and the dotted blocks are selectable.
Detector
Peak
shows one of the four identical
Figure-4 Dual Rail Interface with Clock Recovery
Driver
Line
18). In Software Mode, the
Slicer
CLK&Data
Waveform
Recovery
Detector
Transmit
All Ones
Shaper
(DPLL)
LOS
12
RDNn and RCLKn. Data transmitted from TDPn and TDNn appears on
TTIPn and TRINGn at the line interface; data received from the RTIPn
and RRINGn at the line interface are transferred to RDPn and RDNn
while the recovered clock extracting from the received data stream
outputs on RCLKn. In Dual Rail operation, the clock/data recovery mode
is selectable. Dual Rail interface with clock recovery shown in
is a default configuration mode. Dual Rail interface with data recovery is
shown in Figure-5. Pin RDPn and RDNn, in this condition, are raw RZ
slice output and internally connected to an EXOR which is fed to the
RCLKn output for external clock recovery applications.
and TRINGn at the line interface. Data received from the RTIPn and
RRINGn at the line interface appears on RDn while the recovered clock
extracting from the received data stream outputs on RCLKn. When the
device is in single rail interface, the selectable AMI or B8ZS/HDB3 line
encoder/decoder is available and any code violation in the received data
will be indicated at the CVn pin. The Single Rail mode has 2 sub-modes:
Single Rail Mode 1 and Single Rail Mode 2. Single Rail Mode 1, whose
interface is composed of TDn, TCLKn, RDn, CVn and RCLKn, is real-
ized by pulling pin TDNn high for more than 16 consecutive TCLK
cycles. Single Rail Mode 2, whose interface is composed of TDn,
TCLKn, RDn, CVn, RCLKn and BPVIn, is realized by setting bit CRS in
register e-CRS
between them is that, in the latter mode bipolar violation can be inserted
via pin BPVIn if AMI line code is selected.
rized in Table-2. The configuration of the Host (Software) Mode System
Interface is summarized Table-3.
The Dual Rail interface consists of TDPn
In Single Rail mode, data transmitted from TDn appears on TTIPn
The configuration of the Hardware Mode System Interface is summa-
1.
2.
The footprint ‘n’ (n = 0 - 3) indicates one of the four channels.
The first letter ‘e-’ indicates expanded register.
Attenuator
Attenuator
One of Four Identical Channels
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
Jitter
Jitter
2
and bit SING in register e-SING. The difference
HDB3/AMI
HDB3/AMI
Decoder
Encoder
B8ZS/
B8ZS/
1
September 22, 2005
, TDNn, TCLKn, RDPn,
RCLKn
TCLKn
LOSn
TDPn
RDPn
RDNn
TDNn
Figure-4