82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet
82V2044BB
Specifications of 82V2044BB
Related parts for 82V2044BB
82V2044BB Summary of contents
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FEATURES Fully integrated quad T1/E1 short haul line interface which ! supports 100 Ω T1 twisted pair, 120 Ω E1 twisted pair and 75 Ω E1 coaxial applications ! Selectable Single Rail mode or Dual Rail mode and AMI or ...
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IDT82V2044 DESCRIPTION The IDT82V2044 is a single chip, 4-channel T1/E1 short haul PCM transceiver with a reference clock of 1.544 MHz (T1) or 2.048 MHz (E1). The IDT82V2044 contains 4 transmitters and 4 receivers. All the receivers and transmitters can ...
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IDT82V2044 GNDI GNDI 1 DNC DNC O GNDI GNDI 2 DNC DNC O GNDI GNDI 3 DNC DNC O 4 VDDT VDDT VDDT VDDT 5 DNC DNC DNC DNC 6 GNDT GNDT GNDT GNDT 7 DNC DNC ...
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IDT82V2044 1 PIN DESCRIPTION Table-1 Pin Description Pin No. Name Type TQFP144 TTIP0 45 TTIP1 52 TTIP2 57 TTIP3 64 Analog Output TRING0 46 TRING1 51 TRING2 58 TRING3 63 RTIP0 48 RTIP1 55 RTIP2 60 RTIP3 67 Analog Input ...
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IDT82V2044 Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 TCLK0 36 TCLK1 29 I TCLK2 81 TCLK3 74 RD0/RDP0 40 RD1/RDP1 33 RD2/RDP2 77 RD3/RDP3 O 70 CV0/RDN0 High-Z 41 CV1/RDN1 34 CV2/RDN2 76 CV3/RDN3 69 Pin Description PBGA160 ...
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IDT82V2044 Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 RCLK0 39 O RCLK1 32 RCLK2 78 High-Z RCLK3 71 MCLK I 10 LOS0 42 LOS1 35 O LOS2 75 LOS3 68 I MODE2 11 (Pulled to VDDIO/2) MODE1 I ...
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IDT82V2044 Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 MODE0/CODE CS/JAS 87 (Pulled to VDDIO/2) TS2/SCLK ALE/AS TS1/RD/R Pin Description PBGA160 MODE0: Control Mode Select 0 In parallel host mode, the parallel ...
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IDT82V2044 Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 TS0/SDI/WR SDO/RDY/ACK INT Open 82 Drain D7/AD7 28 D6/AD6 27 D5/AD5 I/O 26 D4/AD4 25 LP3/D3/AD3 24 LP2/D2/AD2 High-Z 23 LP1/D1/AD1 22 LP0/D0/AD0 21 ...
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IDT82V2044 Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 A4 12 MC3/A3 13 MC2/ MC1/A1 15 MC0/ 114 CLKE I 115 I TRST 95 Pull-up I TMS 96 Pull-up TCK I 97 Pin Description ...
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IDT82V2044 Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 O TDO 98 High-Z I TDI 99 Pull-up 17 VDDIO - GNDIO - 100 101 102 107 108 109 144 44 53 ...
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IDT82V2044 Table-1 Pin Description (Continued) Pin No. Name Type TQFP144 103 104 105 106 110 111 112 113 117 118 120 121 DNC - 123 124 126 127 129 130 132 133 ...
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IDT82V2044 2 FUNCTIONAL DESCRIPTION 2.1 OVERVIEW The IDT82V2044 is a fully integrated quad short-haul line interface unit, which contains four transmit and receive channels for use in either applications. The receiver performs clock and data recovery. As ...
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IDT82V2044 RTIPn RRINGn Peak Detector TTIPn TRINGn Note: The grey blocks are bypassed and the dotted blocks are selectable. RTIPn RRINGn Peak Detector TTIPn TRINGn Table-2 System Interface Configuration (In Hardware Mode) Pin MCLK Clocked High (≥ 16 MCLK) Clocked ...
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IDT82V2044 Table-3 System Interface Configuration (In Host Mode) Pin MCLK Pin TDNn CRSn in e-CRS Clocked High 0 Clocked Pulse 0 Clocked Pulse 0 Clocked Pulse 1 High Pulse - Low Pulse - Table-4 Active Clock Edge and Active Level ...
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IDT82V2044 to ‘0’ or pulling pin CODE low. AMI rule is enabled by setting bit CODE in register GCF to ‘1’ or pulling pin CODE high. The settings affect all four channels. Line code rule selection for each channel, if ...
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IDT82V2044 2.4.6 ERROR DETECTION The device can detect excessive zeros, bipolar violation and B8ZS/ HDB3 code violation, as shown in Figure-7, the three kinds of errors are reported in both host mode and hardware mode with B8ZS/HDB3 line code rule ...
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IDT82V2044 RCLKn RTIPn 2 RRINGn 1 RDn CVn 2.5 TRANSMITTER In transmit path, data in NRZ format are clocked into the device on TDn and encoded by AMI or B8ZS/HDB3 line code rules when single rail mode is configured or ...
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IDT82V2044 Table-9 Built-in Waveform Template Selection TS2 TS1 TS0 Service Maximum cable loss ...
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IDT82V2044 A R Line Line X NOTE: 1. Pulse T1124 transformer is recommended to be used in Standard (STD) operating temperature range (0°C to 70°C), while Pulse T1114 transformer is recommended to be used in Extended (EXT) ...
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IDT82V2044 surges coupled in the device. The series resistors do not affect the receiver sensitivity, since the receiver impedance is as high as 120 k typically. 2.12 HITLESS PROTECTION SWITCHING (HPS) The IDT82V2044 transceivers include an output driver with high-Z ...
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IDT82V2044 RTIPn RRINGn Peak Detector TTIPn Driver TRINGn RTIPn RRINGn Analog Loopback TTIPn TRINGn RTIPn RRINGn Peak Detector TTIPn TRINGn Functional Description LOS Detector CLK&Data Recovery Slicer (DPLL) Digital Loopback Line Waveform Shaper Transmit All Ones Figure-13 Digital Loopback LOS ...
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IDT82V2044 RTIPn RRINGn Peak Detector TTIPn Line Driver TRINGn RTIPn RRINGn Peak Detector TTIPn Line Driver TRINGn RTIPn RRINGn Peak Detector TTIPn Line Driver TRINGn Functional Description LOS Detector CLK&Data Jitter Recovery Slicer Attenuator (DPLL) Waveform Jitter Attenuator Shaper Transmit ...
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IDT82V2044 RTIPn RRINGn TTIPn TRINGn 2.13.6 INBAND LOOPBACK Inband Loopback is a function that facilitates the system remote diagnosis. When this function is enabled, the chip will detect or generate the Inband Loopback Code. There are two kinds of Inband ...
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IDT82V2044 tored data can be observed digitally at the output pins RCLK0, RD0/ RDP0 and RDN0. LOS detector is still in use in channel 0 for the moni- tored signal. RTIPn RRINGn TTIPn TRINGn G.772 Monitor RTIP0 RRING0 TTIP0 TRING0 ...
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IDT82V2044 2.18 INTERFACE WITH 5 V LOGIC The IDT82V2044 can interface directly with 5 V TTL family devices. The internal input pads are tolerant output from TTL and CMOS family devices. 2.19 HOST INTERFACE The host interface ...
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IDT82V2044 2.20 INTERRUPT HANDLING 2.20.1 INTERRUPT SOURCES There are four kinds of interrupt sources: 1. Status change in register LOS. The analog/digital loss of signal detector continuously monitors the received signal to update the specific bit in register LOS which ...
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IDT82V2044 3 PROGRAMMING INFORMATION 3.1 REGISTER LIST AND MAP There are 23 primary registers (including an Address Pointer Control Register and 16 expanded registers in the device). Whatever the control interface is, 5 address bits are used to set the ...
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IDT82V2044 Table-16 Expanded (Indirect Address Mode) Register List Address Hex Serial Interface A7-A1 Parallel Interface A7-A0 00 XX00000 01 XX00001 02 XX00010 03 XX00011 04 XX00100 05 XX00101 06 XX00110 07 XX00111 08 XX01000 09 XX01001 0A XX01010 0B XX01011 ...
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IDT82V2044 Table-17 Primary Register Map Address Register R/W Bit 7 Default 00H Default 0 01H - ALB R/W R/W Default 0 02H - RLB R/W R/W Default 0 03H - TAO R/W R/W Default 0 ...
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IDT82V2044 Table-17 Primary Register Map (Continued) Address Register R/W Bit 7 Default 10 Hex - TSIA R/W R/W Default 0 11 Hex - TS R/W R/W Default 0 12 Hex - OE R/W R/W Default 0 13 Hex - AIS ...
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IDT82V2044 Table-18 Expanded (Indirect Address Mode) Register Map Address Register R/W Bit 7 Default 00H e-SING R/W Default 01H e-CODE R/W Default 02H e-CRS R/W Default 03H e-RPDN R/W Default 04H e-TPDN R/W Default 05H e-CZER R/W Default 06H e-CODV ...
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IDT82V2044 3.3 REGISTER DESCRIPTION 3.3.1 PRIMARY REGISTERS ID: Device ID Register (R, Address = 00H) Symbol Position Default An 8-bit word is pre-set into the device as the identification and revision number. This number is different with the functional ID[7:0] ...
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IDT82V2044 DFM: Driver Fault Interrupt Mask Register (R/W, Address = 07H) Symbol Position Default 0 = Normal operation. - DFM.7-4 0000 1 = Reserved Driver fault interrupt not allowed. (Default) DFM[3:0] DFM.3-0 0000 1 = Driver fault interrupt ...
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IDT82V2044 LAC: LOS/AIS Criteria Configuration Register (R/W, Address = 0DH) Symbol Position Default 0 = Normal operation. - LAC.7-4 0000 1 = Reserved. For E1 mode, the criterion is selected as below G.775 (Default) LAC[3:0] LAC.3-0 0000 1 ...
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IDT82V2044 TS: Transmit Template Select Register (R/W, Address = 11H) Symbol Position Default 0 = Normal operation. (Default) - TS.7-3 00000 1 = Reserved. TS[2:0] select one of eight built-in transmit template for different applications. TS[2-0] TS.2-0 000 OE: Output ...
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IDT82V2044 3.3.2 EXPANDED REGISTER DESCRIPTION e-SING: Single Rail Mode Setting Register (R/W, Expanded Address = 00H) Symbol Position Default 0 = Normal operation. - SING.7-4 0000 1 = Reserved Pin TDNn selects single rail mode or dual rail ...
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IDT82V2044 e-CODV: Code Violation Detect Enable/Disable Register (R/W, Expanded Address = 06H) Symbol Position Default 0 = Normal operation. - CODV.7-4 0000 1 = Reserved Code Violation Detect enable for B8ZS/HDB3 decoder in single rail mode. (Default) CODV[3:0] ...
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IDT82V2044 e-LBDC: Inband Loopback Deactivation Code Register Symbol Position Default LBDC[7:0] = 8-bit (or 4-bit) repeating deactivate code is programmed with the length limitation set by LBDL[1:0] bits. LBDC[7:1] = 7-bit repeating deactivate code is programmed with the length limitation ...
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IDT82V2044 4 IEEE STD 1149.1 JTAG TEST ACCESS PORT The IDT82V2044 supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction registers plus a Test Access Port (TAP) ...
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IDT82V2044 Table-19 Instruction Register Description IR Code Instruction The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is placed between TDI and TDO. The signal ...
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IDT82V2044 Table-21 Boundary Scan Register Description (Continued) Bit No. Bit Symbol Pin Signal 16 PIOS N/A 17 TCLK1 TCLK1 18 TDP1 TDP1 19 TDN1 TDN1 20 RCLK1 RCLK1 21 RDP1 RDP1 22 RDN1 RDN1 23 HZEN1 N/A 24 LOS1 LOS1 ...
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IDT82V2044 Table-21 Boundary Scan Register Description (Continued) Bit No. Bit Symbol Pin Signal 57 MODE0 MODE0 (1) 58 LOG0 LOG0 59 LOG0 LOG0 60 LOG0 LOG0 (2) 61 MASK MASK 62 MASK MASK 63 MASK MASK (3) 64 LOG1 LOG1 ...
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IDT82V2044 Table-22 TAP Controller State Description State In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction register with the IDCODE instruction. Test Logic Reset Regardless of the ...
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IDT82V2044 Table-22 TAP Controller State Description (Continued) State This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR Exit1-IR state, which terminates the ...
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IDT82V2044 ABSOLUTE MAXIMUM RATING Symbol VDDA, VDDD Core Power Supply VDDIO0, VDDIO1 I/O Power Supply VDDT0-3 Transmit Power Supply Input Voltage, any digital pin Vin Input Voltage ESD Voltage, any pin Transient Latch-up Current, any pin Iin Input Current, any ...
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IDT82V2044 POWER CONSUMPTION Symbol E1, 3 Ω Load 50% ones density data: 100% ones density data: E1, 3.3 V, 120 Ω Load 50% ones density data: 100% ones density data: E1, 5 Ω Load 50% ones ...
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IDT82V2044 TRANSMITTER CHARACTERISTICS Symbol V (1) Output Pulse Amplitudes o-p E1, 75 Ω load E1, 120 Ω load T1, 100 Ω load V Zero (space) Level O-S E1, 75 Ω load E1, 120 Ω load T1, 100 Ω load Transmit ...
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IDT82V2044 RECEIVER CHARACTERISTICS Symbol ATT Permissible Cable Attenuation (E1: @ 1024 kHz, T1: @ 772 kHz) IA Input Amplitude SIR Signal to Interference Ratio Margin SRE Data Decision Threshold (refer to peak input voltage) Data Slicer Threshold (2) Analog Loss ...
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IDT82V2044 JITTER ATTENUATOR CHARACTERISTICS Symbol f Jitter Transfer Function Corner Frequency (–3 dB) -3dB Host mode Hardware mode Jitter Attenuator ( 400 Hz @ 100 kHz ( ...
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IDT82V2044 TRANSCEIVER TIMING CHARACTERISTICS Symbol MCLK Frequency E1: T1: MCLK Tolerance MCLK Duty Cycle Transmit Path TCLK Frequency E1: T1: TCLK Tolerance TCLK Duty Cycle t1 Transmit Data Setup Time t2 Transmit Data Hold Time Delay time of OE low ...
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IDT82V2044 TCLKn TDn/TDPn BPVIn/TDNn RCLKn RDn/RDPn (CLKE = 1) CVn/RDNn RDn/RDPn (CLKE = 0) CVn/RDNn Transceiver Timing Characteristics t1 Figure-25 Transmit System Interface Timing Figure-26 Receive System Interface Timing 51 QUAD T1/E1 SHORT HAUL ...
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IDT82V2044 JTAG TIMING CHARACTERISTICS Symbol t1 TCK Period t2 TMS to TCK setup Time TDI to TCK Setup Time t3 TCK to TMS Hold Time TCK to TDI Hold Time t4 TCK to TDO Delay Time TCK TMS TDI TDO ...
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IDT82V2044 PARALLEL HOST INTERFACE TIMING CHARACTERISTICS INTEL MODE READ TIMING CHARACTERISTICS Symbol t1 Active RD Pulse Width t2 Active CS to Active RD Setup Time t3 Inactive RD to Inactive CS Hold Time t4 Valid Address to Inactive ALE Setup ...
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IDT82V2044 CS RD ALE(=1) A[4:0] D[7:0] RDY INT Figure-28 Non-Multiplexed Intel Mode Read Timing CS RD ALE AD[7:0] RDY INT Parallel Host Interface Timing Characteristics t2 t1 t13 ADDRESS t6 t8 t15 t2 t1 t11 t12 t13 t16 t4 t6 ...
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IDT82V2044 INTEL MODE WRITE TIMING CHARACTERISTICS Symbol t1 Active WR Pulse Width t2 Active CS to Active WR Setup Time t3 Inactive WR to Inactive CS Hold Time t4 Valid Address to Latch Enable Setup Time (in Multiplexed Mode) t5 ...
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IDT82V2044 MOTOROLA MODE READ TIMING CHARACTERISTICS Symbol t1 Active DS Pulse Width t2 Active CS to Active DS Setup Time t3 Inactive DS to Inactive CS Hold Time t4 Valid R/W to Active DS Setup Time t5 Inactive DS to ...
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IDT82V2044 MOTOROLA MODE WRITE TIMING CHARACTERISTICS Symbol t1 Active DS Pulse Width t2 Active CS to Active DS Setup Time t3 Inactive DS to Inactive CS Hold Time t4 Valid R/W to Active DS Setup Time t5 Inactive DS to ...
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IDT82V2044 SERIAL HOST INTERFACE TIMING CHARACTERISTICS Symbol t1 SCLK High Time t2 SCLK Low Time t3 Active CS to SCLK Setup Time t4 Last SCLK Hold Time to Inactive CS Time t5 CS Idle Time t6 SDI to SCLK Setup ...
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IDT82V2044 JITTER TOLERANCE PERFORMANCE E1 JITTER TOLERANCE PERFORMANCE G.823 IDT82V2044 Test condition: PRBS 2^15-1; Line code rule HDB3 is used. T1 JITTER TOLERANCE PERFORMANCE AT&T62411 IDT82V2044 Test condition: QRSS; Line code rule B8ZS is used. Jitter Tolerance Performance 3 1 ...
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IDT82V2044 JITTER TRANSFER PERFORMANCE E1 JITTER TRANSFER PERFORMANCE G.736 IDT82V2044 Test condition: PRBS 2^15-1; Line code rule HDB3 is used. T1 JITTER TRANSFER PERFORMANCE AT&T62411 GR-253-CORE TR-TSY-000009 IDT82V2044 Test condition: QRSS; Line code rule B8ZS is used. Jitter Transfer Performance ...
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IDT82V2044 ORDERING INFORMATION XXXXXXX IDT Device Type CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 www.idt.com IDT and the IDT logo are trademarks of Integrated Device Technology, Inc Process/ Package Temperature Range for SALES: 1-800-345-7015 ...