82V2044BB IDT, Integrated Device Technology Inc, 82V2044BB Datasheet - Page 20

• Manufacturer Part Number: 82V2044BB
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2044BB

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Not Compliant

surges coupled in the device. The series resistors do not affect the
receiver sensitivity, since the receiver impedance is as high as 120 k
typically.
2.12 HITLESS PROTECTION SWITCHING (HPS)
feature for T1/E1 redundancy applications. This feature reduces the cost
of redundancy protection by eliminating external relays. Details of HPS
are described in relative Application Note.
2.13 LOOPBACK MODE
Digital Loopback, Analog Loopback, Remote Loopback, Dual Loopback
and Inband Loopback. In host mode, these functions are implemented
by programming the registers DLB, ALB, RLB and Inband Loopback
register group respectively. In hardware mode, only Analog Loopback
and Remote Loopback can be selected by pin LPn.
2.13.1 DIGITAL LOOPBACK
can be set in Local Digital Loopback. In this configuration, the data and
clock to be transmitted, after passing the encoder, are looped back to
Jitter Attenuator (if enabled) and decoder in the receive path, then
output on RCLKn, RDn/RDPn and CVn/RDNn. The data to be trans-
mitted are still output on TTIPn and TRINGn while the data received on
RTIPn and RRINGn are ignored. The Loss Detector is still in use.
Figure-13
monitored by the LOS Detector (See
tion
ones signal will be output on RDPn/RDNn. With ATAO enabled, all ones
signal will be also output on TTIPn/TRINGn. AIS insertion can be
enabled by setting AISE bit in register GCF and ATAO can be enabled
by setting register ATAO (default disabled).
2.13.2 ANALOG LOOPBACK
each channel of the device can be configured in Analog Loopback. In
this configuration, the data to be transmitted output from the line driver
are internally looped back to the slicer and peak detector in the receive
path and output on RCLKn, RDn/RDPn and CVn/RDNn. The data to be
IDT82V2044
Functional Description
The IDT82V2044 transceivers include an output driver with high-Z
The device provides five different diagnostic loopback configurations:
By programming the bits of register DLB, each channel of the device
During Digital Loopback, the received signal on the receive line is still
By programming the bits of register ALB or pulling pin LPn high,
for details). In case of a LOS condition and AIS insertion enabled, all
shows the process.
2.4.4 Loss of Signal (LOS) Detec-
Ω
20
transmitted are still output on TTIPn and TRINGn while the data
received on RTIPn and RRINGn are ignored. The LOS Detector (See
2.4.4 Loss of Signal (LOS) Detection
tors the internal looped back data. If a LOS condition on TDPn/TDNn is
expected during Analog Loopback, ATAO should be disabled (default).
Figure-14
directly to do the external analog loopback test. Line impedance loading
is required to conduct the external analog loopback test.
2.13.3 REMOTE LOOPBACK
channel of the device can be configured in Remote Loopback. In this
configuration, the data and clock recovered by the clock and data
recovery circuits are looped to waveform shaper and output on TTIPn
and TRINGn. The jitter attenuator is also included in loopback when
enabled in the transmit or receive path. The received data and clock are
still output on RCLKn, RDn/RDPn and CVn/RDNn while the data to be
transmitted on TCLKn, TDn/TDPn and BPVIn/TDNn are ignored. The
LOs Detector is still in use.
2.13.4 DUAL LOOPBACK
bit RLBn in register RLB to ‘1’. In this configuration, after passing the
encoder, the data and clock to be transmitted are looped back to
decoder directly and output on RCLKn, RDn/RDPn and CVn/RDNn. The
recovered data from RTIPn and RRINGn are looped back to waveform
shaper through JA (if selected) and output on TTIPn and TRINGn. The
LOS Detector is still in use.
2.13.5 TRANSMIT ALL ONES (TAOS)
for more than 16 MCLK cycles. In host mode, TAOS mode is set by
programming register TAO. In addition, automatic TAOS signals are
inserted by setting register ATAO when Loss of Signal occurs. Note that
the TAOS generator adopts MCLK as a timing reference. In order to
assure that the output frequency is within specified limits, MCLK must
have the applicable stability.
TAOS mode with Analog Loopback are shown in Figure-17,
and Figure-19.
The TTIPn and RTIPn, TRINGn and RRINGn cannot be connected
By programming the bits of register RLB or pulling pin LPn low, each
Dual Loopback mode is set by setting bit DLBn in register DLB and
In hardware mode, the TAOS mode is set by pulling pin TCLKn high
The TAOS mode, the TAOS mode with Digital Loopback and the
QUAD T1/E1 SHORT HAUL LINE INTERFACE UNIT
shows the process.
Figure-15
Figure-16
for details) is still in use and moni-
shows the process.
shows the process.
September 22, 2005
Figure-18